TC74HC138AFELF Toshiba

TC74HC138AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC138AP, TC74HC138AF 3-to-8 Line Decoder The TC74HC138A is a high speed CMOS 3-to-8 DECODER 2 TC74HC138AP fabricated with silicon gate C MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( Y0 - Y7 ) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high. G1, G2A , and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems. TC74HC138AF All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features High speed: t = 16 ns (typ.) at V = 5 V pd CC Low power dissipation: I = 4 A (max) at Ta = 25C CC High noise immunity: V = V = 28% V (min) NIH NIL CC Output drive capability: 10 LSTTL loads Symmetrical output impedance: I = I = 4 mA (min) OH OL Weight Balanced propagation delays: t t pLH pHL DIP16-P-300-2.54A : 1.00 g (typ.) Wide operating voltage range: V (opr) = 2 to 6 V CC SOP16-P-300-1.27A : 0.18 g (typ.) Pin and function compatible with 74LS138 Pin Assignment Start of commercial production 1986-11 1 2014-03-01 TC74HC138AP/AF IEC Logic Symbol Truth Table Inputs Outputs Selected Enable Select Output Y0 Y1 Y2 Y3 Y4 Y5 Y 6 Y 7 G1 G2B C B A G2A L X X X X X H H H H H H H H None X H X X X X H H H H H H H H None X X H X X X H H H H H H H H None H L L L L L L H H H H H H H Y 0 H L L L L H H L H H H H H H Y 1 H L L L H L H H L H H H H H Y 2 H L L L H H H H H L H H H H Y3 H L L H L L H H H H L H H H Y 4 H L L H L H H H H H H L H H Y5 H L L H H L H H H H H H L H Y 6 H L L H H H H H H H H H H L Y 7 X: Dont care Logic Diagram 2 2014-03-01