TC7W74FUTE12LF

TC7W74FU/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC7W74FU, TC7W74FK D-Type Flip Flop with Preset and Clear 2 The TC7W74 is a high speed C MOS D Flip Flop fabricated TC7W74FU 2 with silicon gate C MOS technology. It achieves the high speed operation similar to equivalent 2 LSTTL while maintaining the C MOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CLOCK pulse CLEAR and PRESET are independent of the CLOCK and are accomplished by setting the appropriate input to an L level Input is equipped with protection circuits against static discharge or transient excess voltage. (SM8) TC7W74FK Features High speed: f = 77 MHz (typ.) at V = 5 V MAX CC Low power dissipation: I = 2 A (max) at Ta = 25C CC High noise immunity: V = V = 28% V (min) NIH NIL CC Output drive capability: 10 LSTTL loads Symmetrical output impedance: I = I = 4 mA (min) OH OL Balanced propagation delays: t t pLH pHL Wide operating voltage range: V (opr) = 2 to 6 V CC (US8) Weight Marking SSOP8-P-0.65: 0.02 g (typ.) SSOP8-P-0.50A: 0.01 g (typ.) TC7W74FU Part No. 7 W 7 4 Lot No. TC7W74FK Part No. W 7 4 Start of commercial production 1992-02 1 2014-11-18 TC7W74FU/FK Absolute Maximum Ratings (Ta = 25C) Characteristics Symbol Rating Unit Supply voltage range V 0.5 to 7 V CC DC input voltage V 0.5 to V + 0.5 V IN CC DC output voltage V 0.5 to V + 0.5 V OUT CC Input diode current I 20 mA IK Output diode current I 20 mA OK DC output current I 25 mA OUT DC V /ground current I 25 mA CC CC 300 (SM8) Power dissipation P mW D 200 (US8) Storage temperature range T 65 to 150 C stg Lead temperature (10 s) T 260 C L Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (Handling Precautions/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Pin Configuration (top view) V PR CLR Q CC 8 7 6 5 1 2 4 3 CK D GND Q Logic Diagram (7) (5) PR S (1) Q CK C (2) D D (3) (6) Q R CLR 2 2014-11-18