BOOT P GOOD EN SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix 4.5 V to 20 V Input, 15 A, 25 A, 40 A microBuck DC/DC Converter With PMBus Interface FEATURES Versatile - Single supply operation from 4.5 V to 20 V input voltage - Scalable solution with continuous output current of 40 A (SiC450), 25 A (SiC451), 15 A (SiC453) - Adjustable output voltage from 0.3 V to 12 V - Built in 5 V regulator for internal circuits and driver supply - 1 % output voltage accuracy over temperature - Ultrafast transient response LINKS TO ADDITIONAL RESOURCES Highly efficient - 98 % peak efficiency Design Tool Evaluation Design Tools - Optional power save mode Boards Highly configurable DESCRIPTION - PMBus 1.3 compliant with 1 MHz bus speed The SiC45x is a PMBus 1.3 compliant non-isolated DC/DC - Internal NVM buck regulator with integrated MOSFETs. It is capable of - V adjustability and reading resolution of 2 mV OUT supplying up to 40 A (SiC450) continuous output current. Its - Supports over 50 PMBus commands output voltage is digitally adjustable from 0.3 V to 12 V from - Supports in phase or 180 out of phase synchronization a 4.5 V to 20 V input with switching frequencies up to 1.5 - Output voltage source and sink capability MHz. Robust and reliable SiC45x architecture delivers ultrafast transient response - PV , V , I and I and temperature reporting IN OUT IN OUT with minimum output capacitance and tight regulation over a broad load range. The device has integrated internal - Over current protection in pulse-by-pulse mode compensation and is stable with any type of outpu t - Output over and under voltage protection capacitor. The device incorporates a power saving scheme - Over temperature protection with hysteresis that significantly increases light load efficiency. - Differential output remote sensing The SiC45x allows power block configuration programs to be stored in non volatile memory (NVM). Various operation APPLICATIONS parameters can all be locally stored and used to determine Server, cloud, and infrastructure fault behavior. Operation is firmware based and is field Networking, telecom, storage applications upgradable Pinstrap option is also available for default Distributed point of load power architectures configuration without PMBus. DDR memory The SiC45x is available in lead (Pb)-free power enhanced MLP 5 mm x 7 mm package. Axis Title 98 10000 TYPICAL APPLICATION CIRCUIT 96 P 94 GOOD ENABLE 92 1000 INPUT 2.5 V 3.3 V 5 V V PH IN V o o o 4.5 V to 20 V OUT 90 SW PV IN 88 86 100 SiC45x PV V CC SEN+ V = 12 V V V IN DD SEN- 84 F = 600 kHz ADDR sw SALRT RT/SYNC SDA 82 V SET SCL 80 10 0 5 10 15 20 25 30 35 40 I - Output Current (A) OUT Fig. 1 - Typical Application Circuit Fig. 2 - SiC450 Efficiency Curve S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 1 For technical questions, contact: powerictechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 A GND P GND 2nd line eff - Efficiency (%) 1st line 2nd line19 SDA NC 9 NC 8 20 SCL A 7 21 EN GND 22 V BOOT 6 DD GH 5 23 V IN 24 PV PH 4 CC 25 GL PV 3 IN 26 SW 27 SW PV 2 IN 28 SW 29 SW PV 1 IN 30 SW SiC450, SiC451, SiC453 www.vishay.com Vishay Siliconix PIN CONFIGURATION 10 NC 11 V SEN- PV 34 IN 12 V SEN+ 13 P P 33 GOOD GND 14 ADDR 15 V SET P 32 16 A GND GND 17 RT / SYNC SW 31 18 SALRT Fig. 3 - Pin Configuration - Bottom View PIN DESCRIPTION PIN NUMBER SYMBOL DESCRIPTION 1, 2, 3, 34 PV Input voltage for power stage IN 4 PH Phase node, return path of high side gate driver 5GH High side MOSFET gate monitor 6 BOOT Bootstrap voltage for high side gate driver (referenced to PH) 7, 16 A Analog signal return ground GND 8 NC Not used in Vishay device 9 NC Not used in Vishay device 10 NC Not used in Vishay device 11 V Remote sense amplifier negative input connect to output ground SEN- 12 V Remote sense amplifier positive input connect to output SEN+ Power good open-drain output indicating V is within set limits. Connect a pull up resistor typically OUT 13 P GOOD 10 k to V DD 14 ADDR PMBus address programming pin 15 V Output voltage set point by connecting a resistor from V to A SET SET GND Clock synchronization pin. Frequency can be set by connecting a resistor to A . GND 17 RT/SYNC Pending on master / salve configuration, a clock can be send / receive via the pin 18 SALRT PMBus alert. Connect to external host interface if desired 19 SDA PMBus data. Connect to external host interface 20 SCL PMBus clock. Connect to external host interface 21 EN Enable pin. Active high 5 V logic level input 22 V Internal 5 V circuits supply voltage. V is a LDO output, connect a 1 F decoupling capacitor to A DD DD GND 23 V Internal driver supply voltage IN Supply voltage for internal gate drive. PV is a LDO output. Connect a 4.7 F decoupling capacitor to CC 24 PV CC P GND 25 GL Low side MOSFET gate monitor 26 to 31 SW Switch node 32, 33 P Power ground. Common return for internal MOSFETs GND ORDERING INFORMATION PART NUMBER PART MARKING MAXIMUM CURRENT PACKAGE SiC450ED-T1-GE3 SiC450 40 A PowerPAK MLP34-57 SiC450EVB Reference board SiC451ED-T1-GE3 SiC451 25 A PowerPAK MLP34-57 SiC451EVB Reference board SiC453ED-T1-GE3 SiC453 15 A PowerPAK MLP34-57 SiC453EVB Reference board S21-0213-Rev. B, 08-Mar-2021 Document Number: 77863 2 For technical questions, contact: powerictechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000