SiE882DF www.vishay.com Vishay Siliconix N-Channel 25 V (D-S) MOSFET FEATURES PolarPAK D TrenchFET Gen III power MOSFET S 5 6 4 S G 7 3 D 2 Ultra low thermal resistance using top-exposed 8 9 1 D 10 PolarPAK package for double-sided cooling S D Leadframe-based encapsulated package G D - Die not exposed 6 D 7 - Same layout regardless of die size, 100 V S 5 8 S 9 4 G 10 Low Q /Q ratio helps prevent shoot-through gd gs D 3 2 1 100 % R and UIS tested g Top View Bottom View Material categorization: for definitions of compliance Top surface is connected to pins 1, 5, 6, and 10 please see www.vishay.com/doc 99912 APPLICATIONS D PRODUCT SUMMARY VRM V (V) 25 DS R max. ( ) at V = 10 V 0.0014 DC/DC conversion: low side DS(on) GS R max. ( ) at V = 4.5 V 0.0018 DS(on) GS Server V CORE G Q typ. (nC) 46 g a I (A) (package limit) 60 D a I (A) (silicon limit) 229 D S N-Channel MOSFET Configuration Single ORDERING INFORMATION Package PolarPAK Lead (Pb)-free and halogen-free SiE882DF-T1-GE3 ABSOLUTE MAXIMUM RATINGS (T = 25 C, unless otherwise noted) A PARAMETER SYMBOL LIMIT UNIT Drain-source voltage V 25 DS V Gate-source voltage V 20 GS a 60 (package limit) T = 25 C C 229 (silicon limit) a Continuous drain current (T = 150 C) I T = 70 C 60 J C D b, c T = 25 C 47 A b, c T = 70 C 41 A A Pulsed drain current I 100 DM a T = 25 C 60 C Continuous source-drain diode current I S b, c T = 25 C 4.3 A Single pulse avalanche current I 50 AS L = 0.1 mH Avalanche energy E 125 mJ AS T = 25 C 125 C T = 70 C 80 C Maximum power dissipation P W D b, c T = 25 C 5.2 A b, c T = 70 C 3.3 A Operating junction and storage temperature range T , T -55 to +150 J stg C d, e Soldering recommendations (peak temperature) 260 Notes a. Package limited is 60 A b. Surface mounted on 1 x 1 FR4 board c. t = 10 s d. See solder profile (www.vishay.com/doc 73257). The PolarPAK is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is no t required to ensure adequate bottom side solder interconnection e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components S09-1221-Rev. A, 29-Jun-09 Document Number: 65002 1 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000 SiE882DF www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYPICALMAXIMUMUNIT a, b Maximum junction-to-ambient t 10 s R 20 24 thJA Maximum junction-to-case (drain top) R (drain) 0.8 1 C/W thJC Steady state a, c Maximum junction-to-case (source) R (source) 2.2 2.7 thJC Notes a. Surface mounted on 1 x 1 FR4 board b. Maximum under steady state conditions is 68 C/W c. Measured at source pin (on the side of the package) SPECIFICATIONS (T = 25 C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN.TYP.MAX.UNIT Static Drain-source breakdown voltage V V = 0 V, I = 250 A 25 - - V DS GS D V temperature coefficient V /T -25 - DS DS J I = 250 A mV/C D V temperature coefficient V /T --6 - GS(th) GS(th) J Gate-source threshold voltage V V = V , I = 250 A 1 1.7 2.2 V GS(th) DS GS D Gate-source leakage I V = 0 V, V = 20 V - - 100 nA GSS DS GS V = 25 V, V = 0 V - - 1 DS GS Zero gate voltage drain current I A DSS V = 25 V, V = 0 V, T = 55 C - - 10 DS GS J a On-state drain current I V 5 V, V = 10 V 25 - - A D(on) DS GS V = 10 V, I = 20 A - 0.0011 0.0014 GS D a Drain-source on-state resistance R DS(on) V = 4.5 V, I = 20 A - 0.0015 0.0018 GS D a Forward transconductance g V = 15 V, I = 20 A - 125 - S fs DS D b Dynamic Input capacitance C - 6400 - iss V = 12.5 V, V = 0 V, f = 1 MHz Output capacitance C -1400- pF oss DS GS Reverse transfer capacitance C -550- rss V = 12.5 V, V = 10 V, I = 20 A -96 145 DS GS D Total gate charge Q g -46 70 nC Gate-source charge Q -1V = 12.5 V, V = 4.5 V, I = 20 A8- DS GS D gs Gate-drain charge Q -12 - gd Gate resistance R f = 1 MHz 0.2 1.1 2.2 g Turn-on delay time t -45 70 d(on) Rise time t -170255 V = 12.5 V, R = 1.25 , r DD L I 10 A, V = 4.5 V, R = 1 Turn-off delay time t -6D GEN g 5100 d(off) Fall time t -85 130 f ns Turn-on delay time t -20 30 d(on) Rise time t -1525 V = 12.5 V, R = 1.25 , r DD L I 10 A, V = 10 V, R = 1 Turn-off delay time t -4D GEN g 570 d(off) Fall time t -10 15 f Drain-Source Body Diode Characteristics Continuous source-drain diode current I T = 25 C - - 60 S C A a Pulse diode forward current I -- 100 SM Body diode voltage V I = 10 A - 0.8 1.2 V SD S Body diode reverse recovery time t -55 85 ns rr Body diode reverse recovery charge Q - 70 105 nC rr I = 10 A, di/dt = 100 A/s, F T = 25 C Reverse recovery fall time t -25 - J a ns Reverse recovery rise time t -30 - b Notes a. Pulse test pulse width 300 s, duty cycle 2 % b. Guaranteed by design, not subject to production testing Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S09-1221-Rev. A, 29-Jun-09 Document Number: 65002 2 For technical questions, contact: pmostechsupport vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc 91000