VS1011E VLSI VS1011e y Solution VS1011e - MP3 AUDIO DECODER Features Description Decodes MPEG 1.0 & 2.0 audio layer III VS1011e is a single-chip MPEG audio (MP3) de- (MP3: CBR, VBR, ABR) layers I & II coder IC. The circuit contains a high-performance, (MP1, MP2) optional WAV (PCM + IMA 4 low-power DSP processor core VS DSP , work- ADPCM) ing memory, 5 KiB instruction RAM and 0.5 KiB 320 kbit/s MP3 with 12.0 MHz external clock data RAM for user applications, serial control and Streaming support for all audio formats input data interfaces, 4 general purpose I/O pins, Bass and treble controls as well as a high-quality variable-sample-rate stereo Operates with single 12..13 MHz or 24..26 DAC, followed by an earphone amplier and a MHz external clock Internal clock doubler common buffer. Low-power operation High-quality stereo DAC with no phase er- VS1011e receives its input bitstream through a se- ror between channels rial input bus, which it listens to as a system slave. Stereo earphone driver capable of driving a The input stream is decoded and passed through a 30 load digital volume control to an 18-bit oversampling, Separate 2.5 .. 3.6 V operating voltages for multi-bit, sigma-delta DAC. The decoding is con- analog and digital trolled via a serial control bus. In addition to basic Serial control and data interfaces decoding, it is possible to add application specic Can be used as a slave co-processor features, like DSP effects, to the user RAM mem- 5.5 KiB On-chip RAM for user code / data SPI boot for standalone applications ory. New functions may be added with software and 4 GPIO pins VS1011e can boot directly from SPI EEPROM Lead-free and RoHS-compliant packages to run standalone applications without a separate LPQFP-48, BGA-49, and SOIC-28 microcontroller. audio L VS1011 GPIO GPIO Stereo Stereo Ear DAC R phone Driver 4 output X ROM DREQ SO X RAM 4 SI Serial VSDSP Data/ SCLK Control Interface XCS Y ROM XDCS Y RAM Instruction Instruction RAM ROM Version 1.05, 2009-10-06 1VS1011E VLSI VS1011e y Solution CONTENTS Contents 1 License 8 2 Disclaimer 8 3 Denitions 8 4 Characteristics & Specications 9 4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.5 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.6 Switching Characteristics - Boot Initialization . . . . . . . . . . . . . . . . . . . . . . . 11 5 Packages and Pin Descriptions 12 5.1 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.1 LQFP-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.2 BGA-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.3 SOIC-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2.1 LQFP-48 and BGA-49 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . 14 5.2.2 SOIC-28 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Connection Diagram, LQFP-48 16 7 SPI Buses 17 Version 1.05, 2009-10-06 2