X-On Electronics has gained recognition as a prominent supplier of W63AH6NBVADE DRAM across the USA, India, Europe, Australia, and various other global locations. W63AH6NBVADE DRAM are a product manufactured by Winbond. We provide cost-effective solutions for DRAM, ensuring timely deliveries around the world.

W63AH6NBVADE Winbond

W63AH6NBVADE electronic component of Winbond
W63AH6NBVADE Winbond
W63AH6NBVADE DRAM
W63AH6NBVADE  Semiconductors

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Part No. W63AH6NBVADE
Manufacturer: Winbond
Category: DRAM
Description: DRAM 1Gb LPDDR3, x16, 1066MHz
Datasheet: W63AH6NBVADE Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
1: USD 6.8375 ea
Line Total: USD 6.84 
Availability - 0
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0
Ship by Tue. 22 Jul to Thu. 24 Jul
MOQ : 1
Multiples : 1
1 : USD 6.8375
10 : USD 4.576
25 : USD 4.411
100 : USD 3.784
189 : USD 3.773
1134 : USD 3.729
2646 : USD 3.707
5103 : USD 3.608

   
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We are delighted to provide the W63AH6NBVADE from our DRAM category, at competitive rates not only in the United States, Australia, and India, but also across Europe and beyond. A long established and extensive electronic component distribution network has enhanced our global reach and dependability, ensuring cost savings through prompt deliveries worldwide. Client satisfaction is at the heart of our business, where every component counts and every customer matters. Our technical service team is ready to assist you. From product selection to after-sales support, we strive to deliver a seamless and satisfying experience. Are you ready to experience the best in electronic component distribution? Contact X-ON Electronics today and discover why X-On are a preferred choice for the W63AH6NBVADE and other electronic components in the DRAM category and beyond.

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W63AH6NB / W63AH2NB 1Gb LPDDR3 Table of Contents- 1. GENERAL DESCRIPTION ............................................................................................................................................ 5 2. FEATURES .................................................................................................................................................................... 5 3. ORDER INFORMATION ................................................................................................................................................ 5 4. BALL ASSIGNMENT ..................................................................................................................................................... 6 5. BALL CONFIGURATION ............................................................................................................................................... 7 5.1 Ball description ............................................................................................................................................................... 7 5.2 Addressing Table ........................................................................................................................................................... 8 6. BLOCK DIAGRAM ......................................................................................................................................................... 9 7. FUNCTIONAL DESCRIPTION ..................................................................................................................................... 10 7.1 Simplified LPDDR3 State Diagram .............................................................................................................................. 10 7.1.1 Simplified Bus Interface State Diagram ....................................................................................................................... 11 7.2 Power-up, Initialization, and Power-Off ........................................................................................................................ 12 7.2.1 Voltage Ramp and Device Initialization ........................................................................................................................ 12 7.2.2 Initialization after Reset (without Power ramp) ............................................................................................................. 14 7.2.3 Power-off Sequence .................................................................................................................................................... 14 7.2.4 Uncontrolled Power-Off Sequence .............................................................................................................................. 14 7.3 Mode Register Definition .............................................................................................................................................. 15 7.3.1 Mode Register Assignment and Definition ................................................................................................................... 15 7.3.1.1 Mode Register Assignment ............................................................................................................................... 15 7.3.2 MR0 Device Information (MA 7:0 = 00H) ................................................................................................................... 16 7.3.3 MR1 Device Feature 1 (MA 7:0 = 01H) ...................................................................................................................... 16 7.3.3.1 Burst Sequence ................................................................................................................................................ 17 7.3.4 MR2 Device Feature 2 (MA 7:0 = 02H) ...................................................................................................................... 17 7.3.5 MR3 I/O Configuration 1 (MA 7:0 = 03H) ................................................................................................................... 18 7.3.6 MR4 Device Temperature (MA 7:0 = 04H) ................................................................................................................. 18 7.3.7 MR5 Basic Configuration 1 (MA 7:0 = 05H) ............................................................................................................... 18 7.3.8 MR6 Basic Configuration 2 (MA 7:0 = 06H) ............................................................................................................... 19 7.3.9 MR7 Basic Configuration 3 (MA 7:0 = 07H) ............................................................................................................... 19 7.3.10 MR8 Basic Configuration 4 (MA 7:0 = 08H) ............................................................................................................... 19 7.3.11 MR9 (Reserved) (MA 7:0 = 09H) ............................................................................................................................... 19 7.3.12 MR10 Calibration (MA 7:0 = 0AH) ............................................................................................................................. 19 7.3.13 MR11 ODT Control (MA 7:0 = 0BH) .......................................................................................................................... 20 7.3.14 MR12:15 (Reserved) (MA 7:0 = 0CH-OFH) ............................................................................................................... 20 7.3.15 MR16 PASR Bank Mask (MA 7:0 = 10H) .................................................................................................................. 20 7.3.16 MR17 PASR Segment Mask (MA 7:0 = 11H) ............................................................................................................ 20 7.3.17 MR18:31 (Reserved) (MA 7:0 = 12H-1FH) ................................................................................................................ 21 7.3.18 MR32 DQ Calibration Pattern A (MA 7:0 = 20H) ........................................................................................................ 21 7.3.19 MR33:39 ( Do Not Use) (MA 7:0 = 21H-27H) ............................................................................................................. 21 7.3.20 MR40 DQ Calibration Pattern B (MA 7:0 = 28H) ........................................................................................................ 21 7.3.21 MR41 CA Training 1 (MA 7:0 = 29H) ....................................................................................................................... 21 7.3.22 MR42 CA Training 2 (MA 7:0 = 2AH) ....................................................................................................................... 21 7.3.23 MR43:47 ( Do Not Use) (MA 7:0 = 2BH-2FH) ............................................................................................................ 21 7.3.24 MR48 CA Training 3 (MA 7:0 = 30H) ....................................................................................................................... 21 7.3.25 MR49:62 (Reserved) (MA 7:0 = 31H-3EH) ................................................................................................................ 21 7.3.26 MR63 Reset (MA 7:0 = 3FH) ..................................................................................................................................... 21 7.3.27 MR64:255 (Reserved) (MA 7:0 = 40H-FFH) .............................................................................................................. 21 7.4 Command Definitions and Timing Diagrams ................................................................................................................ 22 7.4.1 Activate Command ...................................................................................................................................................... 22 7.4.1.1 8-Bank Device Operation .................................................................................................................................. 22 7.4.2 Command Input Signal Timing Definition ..................................................................................................................... 23 7.4.2.1 CKE Input Setup and Hold Timing .................................................................................................................... 24 7.4.3 Read and Write Access Modes.................................................................................................................................... 24 7.4.4 Burst Read Operation .................................................................................................................................................. 24 Publication Release Date: Dec. 03, 2019 Revision: A01-003 - 1 - W63AH6NB / W63AH2NB 7.4.5 Burst Write Operation .................................................................................................................................................. 29 7.4.5.1 t Calculation ............................................................................................................................................... 30 WPRE 7.4.5.2 t Calculation................................................................................................................................................ 30 WPST 7.4.6 Write Data Mask .......................................................................................................................................................... 32 7.4.7 Precharge Operation ................................................................................................................................................... 33 7.4.7.1 Burst Read Operation Followed by Precharge .................................................................................................. 33 7.4.7.2 Burst Write Followed by Precharge ................................................................................................................... 34 7.4.8 Auto Precharge Operation ........................................................................................................................................... 34 7.4.8.1 Burst Read with Auto-Precharge ....................................................................................................................... 35 7.4.8.2 Burst Write with Auto-Precharge ....................................................................................................................... 35 7.4.8.3 Precharge & Auto Precharge Clarification ......................................................................................................... 36 7.4.9 Refresh command ....................................................................................................................................................... 37 7.4.9.1 Refresh Command Scheduling Separation Requirements ................................................................................. 38 7.4.9.2 Refresh Requirements ...................................................................................................................................... 40 7.4.10 Self Refresh Operation ................................................................................................................................................ 41 7.4.11 Partial Array Self-Refresh (PASR) ............................................................................................................................... 43 7.4.11.1 PASR Bank Masking ......................................................................................................................................... 43 7.4.11.2 PASR Segment Masking................................................................................................................................... 43 7.4.12 Mode Register Read (MRR) Command ....................................................................................................................... 44 7.4.12.1 Temperature Sensor ......................................................................................................................................... 47 7.4.12.2 DQ Calibration .................................................................................................................................................. 48 7.4.13 Mode Register Write (MRW) Command ...................................................................................................................... 49 7.4.13.1 Mode Register Write ......................................................................................................................................... 50 7.4.13.1.1 MRW RESET .................................................................................................................................................... 50 7.4.13.2 Mode Register Write ZQ Calibration Command ................................................................................................ 51 7.4.13.2.1 ZQ External Resistor Value, Tolerance, and Capacitive Loading ...................................................................... 53 7.4.13.3 Mode Register Write CA Training Mode ......................................................................................................... 53 7.4.13.3.1 CA Training Sequence ...................................................................................................................................... 53 7.4.13.4 Mode Register Write WR Leveling Mode ........................................................................................................ 55 7.4.14 On-Die Termination ..................................................................................................................................................... 56 7.4.14.1 ODT Mode register ........................................................................................................................................... 56 7.4.14.2 Asynchronous ODT........................................................................................................................................... 56 7.4.14.3 ODT During Read Operations (RD or MRR)...................................................................................................... 57 7.4.14.4 ODT During Power Down .................................................................................................................................. 57 7.4.14.5 ODT During Self Refresh .................................................................................................................................. 57 7.4.14.6 ODT During Deep Power Down ........................................................................................................................ 57 7.4.14.7 ODT During CA Training and Write Leveling ..................................................................................................... 57 7.4.15 Power-Down ................................................................................................................................................................ 59 7.4.16 Deep Power-Down ...................................................................................................................................................... 64 7.4.17 Input clock stop and frequency change ........................................................................................................................ 65 7.4.18 No Operation Command .............................................................................................................................................. 66 7.5 Truth Tables ................................................................................................................................................................. 67 7.5.1 Command Truth Table ................................................................................................................................................. 67 7.5.2 CKE Truth Table.......................................................................................................................................................... 68 7.5.3 State Truth Tables ....................................................................................................................................................... 69 7.5.4 Data Mask Truth Table ................................................................................................................................................ 72 8. ELECTRICAL CHARACTERISTIC .............................................................................................................................. 73 8.1 Absolute Maximum DC Ratings ................................................................................................................................... 73 8.2 AC & DC Operating Conditions .................................................................................................................................... 73 8.2.1 Recommended DC Operating Conditions .................................................................................................................... 73 8.2.1.1 Recommended DC Operating Conditions ......................................................................................................... 73 8.2.2 Input Leakage Current ................................................................................................................................................. 74 8.2.3 Operating Temperature Range .................................................................................................................................... 74 8.2.4 AC and DC Input Measurement Levels ........................................................................................................................ 74 8.2.4.1 AC and DC Logic Input Levels for Single-Ended Signals................................................................................... 74 8.2.4.1.1 Single-Ended AC and DC Input Levels for CA and CS n Inputs ....................................................................... 74 8.2.4.1.2 Single-Ended AC and DC Input Levels for CKE ................................................................................................ 75 Publication Release Date: Dec. 03, 2019 Revision: A01-003 - 2 -

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WINBOND ELECTRONICS
WINBOND ELECTRONICS CORP AMERICA
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