X-On Electronics has gained recognition as a prominent supplier of W955D8MBYA6I TR DRAM across the USA, India, Europe, Australia, and various other global locations. W955D8MBYA6I TR DRAM are a product manufactured by Winbond. We provide cost-effective solutions for DRAM, ensuring timely deliveries around the world.

W955D8MBYA6I TR Winbond

W955D8MBYA6I TR electronic component of Winbond
W955D8MBYA6I TR Winbond
W955D8MBYA6I TR DRAM
W955D8MBYA6I TR  Semiconductors

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Part No. W955D8MBYA6I TR
Manufacturer: Winbond
Category: DRAM
Description: DRAM 32Mbb HyperRAM x8 166MHz Ind temp 1.8V
Datasheet: W955D8MBYA6I TR Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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MOQ : 1
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1 : USD 5.7736
10 : USD 2.1023
100 : USD 2.0091
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We are delighted to provide the W955D8MBYA6I TR from our DRAM category, at competitive rates not only in the United States, Australia, and India, but also across Europe and beyond. A long established and extensive electronic component distribution network has enhanced our global reach and dependability, ensuring cost savings through prompt deliveries worldwide. Client satisfaction is at the heart of our business, where every component counts and every customer matters. Our technical service team is ready to assist you. From product selection to after-sales support, we strive to deliver a seamless and satisfying experience. Are you ready to experience the best in electronic component distribution? Contact X-ON Electronics today and discover why X-On are a preferred choice for the W955D8MBYA6I TR and other electronic components in the DRAM category and beyond.

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W955D8MBYA 32Mb HyperRAM Table of Contents- 1. FEATURES .................................................................................................................................................................................. 3 2. ORDER INFORMATION .............................................................................................................................................................. 3 3. BALL ASSIGNMENT.................................................................................................................................................................... 4 4. BALL DESCRIPTIONS ................................................................................................................................................................ 5 5. BLOCK DIAGRAM ....................................................................................................................................................................... 6 6. FUNCTIONAL DESCRIPTION ..................................................................................................................................................... 7 6.1 HyperBus Interface ........................................................................................................................................................ 7 7. HYPERBUS TRANSACTION DETAILS ..................................................................................................................................... 10 7.1 Command/Address Bit Assignments ............................................................................................................................ 10 7.2 Read Transactions ....................................................................................................................................................... 14 7.3 Write Transactions (Memory Array Write) .................................................................................................................... 16 7.4 Write Transactions without Initial Latency (Register Write) .......................................................................................... 18 8. MEMORY SPACE ...................................................................................................................................................................... 19 8.1 HyperBus Interface Memory Space addressing ........................................................................................................... 19 8.1.1 Density and Row Boundaries ......................................................................................................................... 19 9. REGISTER SPACE ................................................................................................................................................................... 20 9.1 HyperBus Interface Register Addressing ..................................................................................................................... 20 9.2 Register Space Access ................................................................................................................................................ 20 9.3 Device Identification Registers ..................................................................................................................................... 21 9.4 Configuration Register 0 .............................................................................................................................................. 22 9.4.1 Wrapped Burst ............................................................................................................................................... 23 9.4.2 Initial Latency ................................................................................................................................................. 23 9.4.3 Fixed Latency ................................................................................................................................................ 24 9.4.4 Drive Strength ................................................................................................................................................ 24 9.4.5 Deep Power Down ......................................................................................................................................... 24 9.5 Configuration Register 1 .............................................................................................................................................. 25 9.5.1 Partial Array Refresh ...................................................................................................................................... 25 9.5.2 Hybrid Sleep .................................................................................................................................................. 26 9.5.3 Refresh Multiplier Indicator ............................................................................................................................ 26 10. INTERFACE STATES ................................................................................................................................................................ 27 10.1 Power Conservation Modes ......................................................................................................................................... 27 10.1.1 Interface Standby ........................................................................................................................................... 27 10.1.2 Hybrid Sleep .................................................................................................................................................. 27 10.1.3 Deep Power Down ......................................................................................................................................... 28 11. ELECTRICAL SPECIFICATIONS .............................................................................................................................................. 29 11.1 Absolute Maximum Ratings ......................................................................................................................................... 29 11.2 Operating Ranges ........................................................................................................................................................ 29 11.2.1 Electrical Characteristics and Operating Conditions ...................................................................................... 29 11.2.2 Operating Temperature .................................................................................................................................. 29 11.2.3 IDD Characteristics ........................................................................................................................................ 29 11.2.4 Power-Up Initialization ................................................................................................................................... 31 11.2.5 Hardware Reset ............................................................................................................................................. 32 11.2.6 Capacitance Characteristics .......................................................................................................................... 32 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Jun. 05, 2019 Revision: A01-001 - 1 - W955D8MBYA 12. TIMING SPECIFICATIONS ........................................................................................................................................................ 33 12.1 AC Input-Output Reference Waveform ........................................................................................................................ 33 12.2 AC Test Conditions ...................................................................................................................................................... 33 12.3 AC Characteristics ....................................................................................................................................................... 34 12.3.1 Read Transactions ......................................................................................................................................... 34 12.3.2 Write Transactions ......................................................................................................................................... 37 12.3.3 Hybrid Sleep Timings ..................................................................................................................................... 39 12.3.4 Deep Power down Timings ............................................................................................................................ 39 13. PACKAGE SPECIFICATION ..................................................................................................................................................... 40 14. REVISION HISTORY ................................................................................................................................................................. 41 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission from Winbond. Publication Release Date: Jun. 05, 2019 Revision: A01-001 - 2 -

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:
WINBOND ELECTRONICS
WINBOND ELECTRONICS CORP AMERICA
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