W97BH6MB / W97BH2MB LPDDR2-S4B 2Gb Table of Contents- 1. GENERAL DESCRIPTION ............................................................................................................................................ 6 2. FEATURES .................................................................................................................................................................... 6 3. ORDER INFORMATION ................................................................................................................................................ 6 4. BALL ASSIGNMENT ..................................................................................................................................................... 7 5. BALL CONFIGURATION ............................................................................................................................................... 8 5.1 Ball Description .............................................................................................................................................................. 8 5.2 Addressing Table ........................................................................................................................................................... 9 6. BLOCK DIAGRAM ....................................................................................................................................................... 10 7. FUNCTIONAL DESCRIPTION ..................................................................................................................................... 11 7.1 Simplified LPDDR2 State Diagram .............................................................................................................................. 11 7.1.1 Simplified LPDDR2 Bus Interface State Diagram ......................................................................................................... 12 7.2 Power-up, Initialization, and Power-Off ........................................................................................................................ 13 7.2.1 Power Ramp and Device Initialization .......................................................................................................................... 13 7.2.2 Timing Parameters for Initialization .............................................................................................................................. 15 7.2.3 Power Ramp and Initialization Sequence .................................................................................................................... 15 7.2.4 Initialization after Reset (without Power ramp) ............................................................................................................. 16 7.2.5 Power-off Sequence .................................................................................................................................................... 16 7.2.6 Timing Parameters Power-Off ..................................................................................................................................... 16 7.2.7 Uncontrolled Power-Off Sequence .............................................................................................................................. 16 7.3 Mode Register Definition .............................................................................................................................................. 17 7.3.1 Mode Register Assignment and Definition ................................................................................................................... 17 7.3.1.1 Mode Register Assignment ............................................................................................................................... 17 7.3.2 MR0 Device Information (MA 7:0 = 00H) ................................................................................................................... 18 7.3.3 MR1 Device Feature 1 (MA 7:0 = 01H) ...................................................................................................................... 18 7.3.3.1 Burst Sequence by Burst Length (BL), Burst Type (BT), and Warp Control (WC) .............................................. 19 7.3.3.2 Non Wrap Restrictions ...................................................................................................................................... 19 7.3.4 MR2 Device Feature 2 (MA 7:0 = 02H) ...................................................................................................................... 20 7.3.5 MR3 I/O Configuration 1 (MA 7:0 = 03H) ................................................................................................................... 20 7.3.6 MR4 Device Temperature (MA 7:0 = 04H) ................................................................................................................. 20 7.3.7 MR5 Basic Configuration 1 (MA 7:0 = 05H) ............................................................................................................... 21 7.3.8 MR6 Basic Configuration 2 (MA 7:0 = 06H) ............................................................................................................... 21 7.3.9 MR7 Basic Configuration 3 (MA 7:0 = 07H) ............................................................................................................... 21 7.3.10 MR8 Basic Configuration 4 (MA 7:0 = 08H) ............................................................................................................... 21 7.3.11 MR9 Test Mode (MA 7:0 = 09H) ................................................................................................................................ 21 7.3.12 MR10 Calibration (MA 7:0 = 0AH) ............................................................................................................................. 22 7.3.13 MR16 PASR Bank Mask (MA 7:0 = 10H) .................................................................................................................. 22 7.3.14 MR17 PASR Segment Mask (MA 7:0 = 11H) ............................................................................................................ 23 7.3.15 MR32 DQ Calibration Pattern A (MA 7:0 = 20H) ........................................................................................................ 23 7.3.16 MR40 DQ Calibration Pattern B (MA 7:0 = 28H) ........................................................................................................ 23 7.3.17 MR63 Reset (MA 7:0 = 3FH): MRW only ................................................................................................................... 23 7.4 Command Definitions and Timing Diagrams ................................................................................................................ 24 7.4.1 Activate Command ...................................................................................................................................................... 24 7.4.1.1 Activate Command Cycle: tRCD = 3, tRP = 3, tRRD = 2 ................................................................................... 24 7.4.1.2 tFAW Timing ..................................................................................................................................................... 25 7.4.1.3 Command Input Setup and Hold Timing............................................................................................................ 25 7.4.1.4 CKE Input Setup and Hold Timing .................................................................................................................... 26 7.4.2 Read and Write Access Modes.................................................................................................................................... 26 7.4.3 Burst Read Command ................................................................................................................................................. 26 7.4.3.1 Data Output (Read) Timing (tDQSCKmax) ........................................................................................................ 27 7.4.3.2 Data Output (Read) Timing (tDQSCKmin) ......................................................................................................... 28 7.4.3.3 Burst Read: RL = 5, BL = 4, tDQSCK > tCK ...................................................................................................... 28 7.4.3.4 Burst Read: RL = 3, BL = 8, tDQSCK < tCK ...................................................................................................... 29 Publication Release Date: Aug. 19, 2019 Revision: A01-002 - 1 - W97BH6MB / W97BH2MB 7.4.3.5 LPDDR2: tDQSCKDL Timing ............................................................................................................................ 29 7.4.3.6 LPDDR2: tDQSCKDM Timing ........................................................................................................................... 30 7.4.3.7 LPDDR2: tDQSCKDS Timing............................................................................................................................ 30 7.4.3.8 Burst Read Followed by Burst Write: RL = 3, WL = 1, BL = 4 ............................................................................ 31 7.4.3.9 Seamless Burst Read: RL = 3, BL= 4, tCCD = 2 ............................................................................................... 31 7.4.4 Reads Interrupted by a Read ....................................................................................................................................... 32 7.4.4.1 Read Burst Interrupt Example: RL = 3, BL= 8, tCCD = 2 ................................................................................... 32 7.4.5 Burst Write Operation .................................................................................................................................................. 32 7.4.5.1 Data Input (Write) Timing .................................................................................................................................. 33 7.4.5.2 Burst Write: WL = 1, BL= 4 ............................................................................................................................... 33 7.4.5.3 Burst Write Followed by Burst Read: RL = 3, WL= 1, BL= 4 .............................................................................. 34 7.4.5.4 Seamless Burst Write: WL= 1, BL = 4, tCCD = 2............................................................................................... 34 7.4.6 Writes Interrupted by a Write ....................................................................................................................................... 35 7.4.6.1 Write Burst Interrupt Timing: WL = 1, BL = 8, tCCD = 2 .................................................................................... 35 7.4.7 Burst Terminate ........................................................................................................................................................... 35 7.4.7.1 Burst Write Truncated by BST: WL = 1, BL = 16 ............................................................................................... 36 7.4.7.2 Burst Read Truncated by BST: RL = 3, BL = 16 ................................................................................................ 36 7.4.8 Write Data Mask .......................................................................................................................................................... 37 7.4.8.1 Write Data Mask Timing .................................................................................................................................... 37 7.4.9 Precharge Operation ................................................................................................................................................... 38 7.4.9.1 Bank Selection for Precharge by Address Bits .................................................................................................. 38 7.4.10 Burst Read Operation Followed by Precharge ............................................................................................................. 38 7.4.10.1 Burst Read Followed by Precharge: RL = 3, BL = 8, RU(tRTP(min)/tCK) = 2 .................................................... 39 7.4.10.2 Burst Read Followed by Precharge: RL = 3, BL = 4, RU(tRTP(min)/tCK) = 3 .................................................... 39 7.4.11 Burst Write Followed by Precharge ............................................................................................................................. 40 7.4.11.1 Burst Write Followed by Precharge: WL = 1, BL = 4 .......................................................................................... 40 7.4.12 Auto Precharge Operation ........................................................................................................................................... 41 7.4.13 Burst Read with Auto-Precharge ................................................................................................................................. 41 7.4.13.1 Burst Read with Auto-Precharge: RL = 3, BL = 4, RU(tRTP(min)/tCK) = 2 ........................................................ 41 7.4.14 Burst Write with Auto-Precharge .................................................................................................................................. 42 7.4.14.1 Burst Write with Auto-Precharge: WL = 1, BL = 4 .............................................................................................. 42 7.4.14.2 Precharge & Auto Precharge Clarification ......................................................................................................... 43 7.4.15 Refresh Command ...................................................................................................................................................... 44 7.4.15.1 Command Scheduling Separations Related to Refresh ..................................................................................... 45 7.4.16 LPDDR2 SDRAM Refresh Requirements .................................................................................................................... 45 7.4.16.1 Definition of tSRF .............................................................................................................................................. 46 7.4.16.2 Regular, Distributed Refresh Pattern ................................................................................................................. 48 7.4.16.3 Allowable Transition from Repetitive Burst Refresh ........................................................................................... 48 7.4.16.4 NOT-Allowable Transition from Repetitive Burst Refresh .................................................................................. 49 7.4.16.5 Recommended Self-Refresh Entry and Exit ...................................................................................................... 49 7.4.16.6 All Bank Refresh Operation ............................................................................................................................... 50 7.4.16.7 Per Bank Refresh Operation ............................................................................................................................. 50 7.4.17 Self Refresh Operation ................................................................................................................................................ 51 7.4.18 Partial Array Self-Refresh: Bank Masking .................................................................................................................... 52 7.4.19 Partial Array Self-Refresh: Segment Masking .............................................................................................................. 52 7.4.20 Mode Register Read Command .................................................................................................................................. 53 7.4.20.1 Mode Register Read Timing Example: RL = 3, tMRR = 2 .................................................................................. 54 7.4.20.2 Read to MRR Timing Example: RL = 3, tMRR = 2 ............................................................................................ 55 7.4.20.3 Burst Write Followed by MRR: RL = 3, WL = 1, BL = 4 ..................................................................................... 55 7.4.21 Temperature Sensor.................................................................................................................................................... 56 7.4.21.1 Temperature Sensor Timing ............................................................................................................................. 57 7.4.21.2 DQ Calibration .................................................................................................................................................. 57 7.4.21.3 MR32 and MR40 DQ Calibration Timing Example: RL = 3, tMRR = 2 ............................................................... 58 7.4.22 Mode Register Write Command................................................................................................................................... 59 7.4.22.1 Mode Register Write Timing Example: RL = 3, tMRW = 5 ................................................................................. 59 7.4.22.2 Truth Table for Mode Register Read (MRR) and Mode Register Write (MRW) .................................................. 59 Publication Release Date: Aug. 19, 2019 Revision: A01-002 - 2 -