Product Information

W9812G6KH-5 TR

W9812G6KH-5 TR electronic component of Winbond

Datasheet
DRAM 128Mb SDR SDRAM x16, 200MHz T&R

Manufacturer: Winbond
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1000: USD 1.7125 ea
Line Total: USD 1712.5

0 - Global Stock
MOQ: 1000  Multiples: 1000
Pack Size: 1000
Availability Price Quantity
0 - WHS 1


Ships to you between Thu. 30 May to Mon. 03 Jun

MOQ : 1000
Multiples : 1000
1000 : USD 1.5662
2000 : USD 1.5306
5000 : USD 1.5187
10000 : USD 1.495
25000 : USD 1.495

     
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W9812G6KH 2M 4 BANKS 16 BITS SDRAM Table of Contents- 1. GENERAL DESCRIPTION .............................................................................................................. 3 2. FEATURES ...................................................................................................................................... 3 3. ORDER INFORMATION .................................................................................................................. 3 4. PIN CONFIGURATION .................................................................................................................... 4 5. PIN DESCRIPTION ......................................................................................................................... 5 6. BLOCK DIAGRAM ........................................................................................................................... 6 7. FUNCTIONAL DESCRIPTION ........................................................................................................ 7 7.1 Power Up and Initialization ................................................................................................. 7 7.2 Programming Mode Register .............................................................................................. 7 7.3 Bank Activate Command .................................................................................................... 7 7.4 Read and Write Access Modes .......................................................................................... 7 7.5 Burst Read Command ........................................................................................................ 8 7.6 Burst Write Command ......................................................................................................... 8 7.7 Read Interrupted by a Read................................................................................................ 8 7.8 Read Interrupted by a Write ................................................................................................ 8 7.9 Write Interrupted by a Write ................................................................................................ 8 7.10 Write Interrupted by a Read ................................................................................................ 8 7.11 Burst Stop Command .......................................................................................................... 8 7.12 Addressing Sequence of Sequential Mode......................................................................... 9 7.13 Addressing Sequence of Interleave Mode .......................................................................... 9 7.14 Auto-precharge Command................................................................................................ 10 7.15 Precharge Command ........................................................................................................ 10 7.16 Self Refresh Command ..................................................................................................... 10 7.17 Power Down Mode ............................................................................................................ 11 7.18 No Operation Command ................................................................................................... 11 7.19 Deselect Command .......................................................................................................... 11 7.20 Clock Suspend Mode ........................................................................................................ 11 8. OPERATION MODE ...................................................................................................................... 12 9. ELECTRICAL CHARACTERISTICS ............................................................................................. 13 9.1 Absolute Maximum Ratings .............................................................................................. 13 9.2 Recommended DC Operating Conditions ........................................................................ 13 9.3 Capacitance ...................................................................................................................... 14 9.4 DC Characteristics ............................................................................................................ 14 9.5 AC Characteristics and Operating Condition .................................................................... 15 10. TIMING WAVEFORMS .................................................................................................................. 17 10.1 Command Input Timing ..................................................................................................... 17 10.2 Read Timing ...................................................................................................................... 18 10.3 Control Timing of Input/Output Data ................................................................................. 19 10.4 Mode Register Set Cycle .................................................................................................. 20 Publication Release Date: Feb. 22, 2017 Revision: A05 - 1 - W9812G6KH 11. OPERATING TIMING EXAMPLE .................................................................................................. 21 11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) .......................................... 21 11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) ............... 22 11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) .......................................... 23 11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) ............... 24 11.5 Interleaved Bank Write (Burst Length = 8) ....................................................................... 25 11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ............................................ 26 11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) ................................................... 27 11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ....................................... 28 11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3) ............................................ 29 11.10 Auto Precharge Write (Burst Length = 4) ......................................................................... 30 11.11 Auto Refresh Cycle ........................................................................................................... 31 11.12 Self Refresh Cycle ............................................................................................................ 32 11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ................................. 33 11.14 Power Down Mode ............................................................................................................ 34 11.15 Auto-precharge Timing (Read Cycle) ............................................................................... 35 11.16 Auto-precharge Timing (Write Cycle) ............................................................................... 36 11.17 Timing Chart of Read to Write Cycle ................................................................................ 37 11.18 Timing Chart of Write to Read Cycle ................................................................................ 37 11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) ............................................... 38 11.20 Timing Chart of Burst Stop Cycle (Precharge Command) ................................................ 38 11.21 CKE/DQM Input Timing (Write Cycle) .............................................................................. 39 11.22 CKE/DQM Input Timing (Read Cycle) .............................................................................. 40 12. PACKAGE SPECIFICATION ......................................................................................................... 41 13. REVISION HISTORY ..................................................................................................................... 42 Publication Release Date: Feb. 22, 2017 Revision: A05 - 2 -

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:
Winbond Elec
WINBOND ELECTRONICS
WINBOND ELECTRONICS CORP AMERICA

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