LogiCORE IP LTE PUCCH Receiver v2.0 PB018 (v2.0) November 18, 2015 Product Brief LogiCORE IP Facts Table Introduction Core Specifics The Xilinx LogiCORE IP LTE Physical Uplink UltraScale+ Families Control Channel (PUCCH) Receiver implements Supported UltraScale Architecture (1) Device Family Zynq-7000 All Programmable SoC an AXI4-Stream compliant, high-performance, 7 Series optimized block for the 3GPP TS 36.211 v9.0.0 Supported User Physical uplink control channel. The data and AXI4-Stream Interfaces control for the core are input on independent Provided with Core AXI4-Stream channels as slave interfaces and Design Files Encrypted RTL the resulting status is output on an AXI4-Stream master interface. Example Design Not Provided Test Bench VHDL Additional Documentation Constraints File Not Provided VHDL Behavioral Simulation A product guide is available for this core. Access VHDL or Verilog Structural Model C Model to this material may be requested by clicking on Supported this registration link: www.xilinx.com/member/ N/A S/W Driver pucch eval/index.htm. (2) Tested Design Flows Design Entry Vivado Design Suite Features For supported simulators, see the Simulation Xilinx Design Tools: Release Notes Guide. Physical Uplink Control Channel Receiver Synthesis Vivado Synthesis for 3GPP TS 36.211 v9.0.0 Support TDD/FDD compliant Provided by Xilinx at the Xilinx Support web page Supports 1, 2 or 4 antenna operation Notes: Supports all format types including Mixed 1. For a complete listing of supported devices, see the Vivado IP Format catalog. 2. For the supported versions of the tools, see the Supports both normal and shortened slots Xilinx Design Tools: Release Notes Guide. Supports normal and extended Cyclic Prefix Fully optimized for speed and area Fully synchronous design using a single clock Bit-accurate C model Compliant with all required conformance tests (3GPP TS36.141 Base Station conformance testing) Customer demonstration test bench Copyright 20142015 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, ARM, ARM1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the EU and other countries. MATLAB and Simulink are registered trademarks of The MathWorks, Inc. All other trademarks are the property of their respective owners. LTE PUCCH Receiver v2.0 www.xilinx.com 1 PB018 (v2.0) November 18, 2015 Product SpecificationProduct Brief Applications The LTE PUCCH Receiver core provides a receiver solution for the 3GPP 36.211 Physical Uplink Control Channel (PUCCH). The architecture has been designed to provide efficient use of the FPGA resources while also offering a low bandwidth processor interface to reduce system-level overhead. Timing critical operations are performed by the FPGA. Technical Support Xilinx provides technical support at the Xilinx Support web page for this LogiCORE IP product when used as described in the product documentation. Xilinx cannot guarantee timing, functionality, or support if you do any of the following: Implement the solution in devices that are not defined in the documentation. Customize the solution beyond that allowed in the product documentation. Change any section of the design labeled DO NOT MODIFY. To contact Xilinx Technical Support, navigate to the Xilinx Support web page. Licensing and Ordering Information This Xilinx LogiCORE IP module is provided under the terms of the Xilinx Core License Agreement. The module is shipped as part of the Vivado Design Suite. For full access to all core functionalities in simulation and in hardware, you must purchase a license for the core. Contact your local Xilinx sales representative for information about pricing and availability. For more information, visit the LTE PUCCH product web page. Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page. For information on pricing and availability of other Xilinx LogiCORE IP modules and tools, contact your local Xilinx sales representative. LTE PUCCH Receiver v2.0 www.xilinx.com 2 Send Feedback PB018 (v2.0) November 18, 2015