Product Information

Z8L18020FSG

Z8L18020FSG electronic component of ZiLOG

Datasheet
ZiLOG Microprocessors - MPU 20MHz Low Pow S180
Manufacturer: ZiLOG
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 19.1423 ea
Line Total: USD 19.14

640 - Global Stock
Ships to you between
Fri. 17 May to Tue. 21 May
MOQ: 1  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
629 - WHS 1


Ships to you between Fri. 17 May to Tue. 21 May

MOQ : 1
Multiples : 1
1 : USD 19.136
10 : USD 17.7905
25 : USD 13.9265
100 : USD 13.8575
264 : USD 13.8115
528 : USD 13.731
1056 : USD 13.34
2508 : USD 13.2595
5016 : USD 12.8455

Read More Specifications

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Series
Core
Data Bus Width
Maximum Clock Frequency
Interface Type
Operating Supply Voltage
Number of Cores
Mounting Style
Package / Case
Minimum Operating Temperature
Maximum Operating Temperature
Packaging
Brand
Number Of Timers
On-Chip Adc
Factory Pack Quantity :
Cnhts
Hts Code
I/O Voltage
Mxhts
Number Of Timers/Counters
Processor Series
Taric
Watchdog Timers
LoadingGif

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Additional Infomation About Product

24 .+/+0 4 241&7%6 52 %+(+% 6+10 < 5 < . 0* 0% & < /+%41241% 5514 1(( 45 ( 56 4 : %76+10 219 4 5 8 4 /1& .19 /+ ( 674 5 Code Compatible with ZiLOG Z80 CPU Two 16-Bit Counter/Timers Extended Instructions Two Enhanced UARTs (up to 512 Kbps) Two Chain-Linked DMA Channels Clock Speeds: 10, 20, 33 MHz Low Power-Down Modes Operating Range: 5V (3.3V 20 MHz) On-Chip Interrupt Controllers Operating Temperature Range: 0C to +70C Three On-Chip Wait-State Generators 40C to +85C Extended Temperature Range On-Chip Oscillator/Generator Three Packaging Styles 68-Pin PLCC Expanded MMU Addressing (Up to 1 MB) 64-Pin DIP Clocked Serial I/O Port 80-Pin QFP ) 0 4 . & 5%4+26+10 three modes intended to further reduce power consumption. The enhanced Z8S180/Z8L180 significantly improves on Power consumption during 56 0& Mode is reduced to previous Z80180 models, while still providing full back- 10 A by stopping the external oscillators and internal ward compatibility with existing ZiLOG Z80 devices. The clock. The 5. 2 mode reduces power by placing the CPU Z8S180/Z8L180 now offers faster execution speeds, pow- into a stopped state, consuming less current while the on- er-saving modes, and EMI noise reduction. chip I/O devices still operate. The 5 56 / 5612 mode This enhanced Z180 design also incorporates additional places both the CPU and the on-chip peripherals into a feature enhancements to the ASCIs, DMAs, and 56 0& stopped mode, reducing power consumption even further. mode power consumption. With the addition of ESCC-like A new clock-doubler feature in the Z8S180/Z8L180 allows Baud Rate Generators (BRGs), the two ASCIs offer the flex- the internal clock speed to be twice the external clock speed. ibility and capability to transfer data asynchronously at rates As a result, system cost is reduced by allowing the use of of up to 512 Kbps. In addition, the ASCI receiver features lower-cost, lower-frequency crystals. a 4-byte first in/first out (FIFO) buffer which reduces the likelihood of overrun errors. The DMAs have been modified The Enhanced Z180 is housed in 80-pin QFP, 68-pin PLCC, to allow for chain-linking of the two DMA channels when and 64-pin DIP packages. set to take their DMA requests from the same peripherals device. This feature allows for nonstop DMA operation be- 0QVG All Signals with an overline are active Low. For exam- tween the two DMA channels. ple: B/W, in which WORD is active Low or B/W, in which BYTE is active Low. Not only does the Z8S180/Z8L180 consume less power dur- ing normal operations than the previous model, it offers &5 </2 < 5 < . PJCPEGF < /KETQRTQEGUUQT ZiLOG ) 0 4 . & 5%4+26+10 %QPVKPWGF Power connections follow the conventional descriptions be- low: %QPPGEVKQP %KTEWKV &GXKEG 2QYGT 8 8 %% && )TQWPF )0& 8 55 WU 5VCVG %QPVTQN +PVGTTWRV 6KOKPI 2*+ )GPGTCVQT %27 &4 3 KV &/ %U 2TQITCOOCDNG 6 6 0& 176 4GNQCF 6KOGTU 6:5 6: %NQEMGF 5GTKCN + 1 4:5 %65 %- &4 3 2QTV U PEJTQPQWU 5%+ %-5 4: %JCPPGN 465 %65 &%& 6: //7 U PEJTQPQWU %- 6 0& 5%+ 4: %JCPPGN 8 && FFTGUU &CVC WHHGT WHHGT 8 55 & & (KIWTG < 5 < . (WPEVKQPCN NQEM &KCITCO 2 4 . + / + 0 4 &5 </2 :6 . :6 . FFTGUU WU KV 4 5 6 4& 94 &CVC WU KV / /4 3 +143 * .6 9 +6 754 3 75 %- 4(5* 56 0/+ +06 +06 +06

HS Compliance

Tariff Desc

8542.31.00 52 No ..CMOS and MOS Microprocessors (MPU), Microcontrollers (MCU) and Digital Signal Processors (DSP)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits Digital.

Zilog may also be referenced as

ZIL
ZILOG
Zilog (VA)
ZILOG ELECTRONICS
Zilog, an IXYS Company

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