CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters Rev 2B Data Sheet CDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters FEATURES General Description n 10-bit resolution The CDK2308 is a high performance, low power dual Analog-to-Digital Con- n 20/40/65/80MSPS maximum sampling rate verters (ADC). The ADC employs internal reference circuitry, a CMOS control n Ultra-low power dissipation: 24/43/65/78mW interface and CMOS output data, and is based on a proprietary structure. Digital error correction is employed to ensure no missing codes in the com- n 61.6dB SNR at 80MSPS and 8MHz F IN plete full scale range. n Internal reference circuitry n Several idle modes with fast startup times exist. Each channel can indepen- 1.8V core supply voltage dently be powered down and the entire chip can either be put in Standby n 1.7V 3.6V I/O supply voltage Mode or Power Down mode. The different modes are optimized to allow the n Parallel CMOS output user to select the mode resulting in the smallest possible energy consumption n 64-pin QFN package during idle mode and startup. n Dual channel The CDK2308 has a highly linear THA optimized for frequencies up to Nyquist. n Pin compatible with CDK2307 The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave and CMOS clock inputs. APPLICATIONS n Medical Imaging Functional Block Diagram n Portable Test Equipment n Digital Oscilloscopes n IF Communication CLK EXT 10 10 Ordering Information Part Number Speed Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method CDK2308AILP64 20MSPS QFN-64 Yes Yes -40C to +85C Tray CDK2308BILP64 40MSPS QFN-64 Yes Yes -40C to +85C Tray CDK2308CILP64 65MSPS QFN-64 Yes Yes -40C to +85C Tray CDK2308DILP64 80MSPS QFN-64 Yes Yes -40C to +85C Tray Moisture sensitivity level for all parts is MSL-2A. Exar Corporation www.exar.com 48720 Kato Road, Fremont CA 94538, USA Tel. +1 510 668-7000 - Fax. +1 510 668-7001 CLKP CLKNCDK2308 Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters Rev 2B Data Sheet Pin Configuration QFN-64, TQFP-64 1 48 2 47 3 46 4 45 N/C 5 44 N/C 6 43 N/C CDK2308 7 42 CLK EXT QFN-64 8 41 9 40 10 39 11 38 12 37 DVSSCLK 13 36 DVDDCLK 14 35 CLKP 15 34 CLKN 16 33 Pin Assignments Pin No. Pin Name Description 1, 18, 23 DV Digital and I/O-ring pre driver supply voltage, 1.8V DD 2 CM EXT Common Mode voltage output 3, 9, 12 AV Analog supply voltage, 1.8V DD 4, 5, 8 AV Analog ground SS 6, 7 IP0, IN0 Analog input Channel 0 (non-inverting, inverting) 10, 11 IP1, IN1 Analog input Channel 1 (non-inverting, inverting) 13 DV Clock circuitry ground SSCLK 14 DV Clock circuitry supply voltage, 1.8V DDCLK 15 CLKP Clock input, non-inverting (Format: LVDS, PECL, CMOS/TTL, Sine Wave) 16 CLKN Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground 17, 64 DV Digital circuitry ground SS 19 CLK EXT EN CLK EXT signal enabled when low (zero). Tristate when high. 20 D Data format selection. 0: Offset Binary, 1: Two s Complement FRMT 21 PD N Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up, always apply Power Down mode before using Active mode to reset chip. 22 OE N 1 Output Enable Channel 0. Tristate when high 24, 41, 58 O I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V. VDD 25, 40, 57 O Ground for I/O ring VSS 2009-2013 Exar Corporation 2/15 Rev 2B 17 64 18 63 CLK EXT EN 19 62 20 61 21 60 22 59 23 58 24 57 56 25 55 N/C 26 N/C 27 54 53 N/C 28 52 29 51 D0 5 30 50 D0 4 31 32 49 D0 3