XRT75L04 FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER JULY 2006 REV. 1.0.4 GENERAL DESCRIPTION Provides low jitter clock outputs for either DS3,E3 or STS-1 rates. The XRT75L04 is a four-channel fully integrated Line TRANSMITTER: Interface Unit (LIU) with Jitter Attenuator for E3/DS3/ STS-1 applications. It incorporates four independent Compliant with Telcordia GR-499, GR-253 and Receivers, Transmitters and Jitter Attenuators in a ANSI T1.102 Specification for transmit pulse single 176 pin LQFP package. Tri-state Transmit output capability for redundancy Each channel of the XRT75L04 can be configured to applications operate in E3 (34.368 MHz), DS3 (44.736 MHz) or Transmitters can be turned on or off. STS-1 (51.84 MHz) rates that are independent of JITTER ATTENUATOR: each other. Each transmitter can be turned off and tri- stated for redundancy support and for conserving On chip advanced crystal-less Jitter Attenuator. power. Jitter Attenuators can be selected in Receive or The XRT75L04s differential receivers provide high Transmit paths. noise interference margin and are able to receive the Compliant with jitter transfer template outlined in data over 1000 feet of cable or with up to 12 dB of ITU G.751, G.752, G.755, GR-253 and GR-499- cable attenuation. CORE,1995 standards. The XRT75L04 incorporates an advanced crystal- Meets ETSI TBR 24 Jitter Transfer Requirements. less jitter attenuator per channel that can be selected either in the transmit or receive path. The jitter 16 or 32 bits selectable FIFO size. attenuator performance meets the ETSI TBR-24 and Meets the Wander specifications described in Telcordia GR-499, GR-253 specifications. T1.105.03b. The XRT75L04 provides both Serial Microprocessor Jitter Attenuators can be disabled. Interface as well as Hardware mode for programming and control. CONTROL AND DIAGNOSTICS: The XRT75L04 supports local, remote and digital Serial Microprocessor Interface for control and loop-backs. The XRT75L04 also contains an on- configuration. board Pseudo Random Binary Sequence (PRBS) Supports optional internal Transmit Driver generator and detector with the ability to insert and Monitoring. detect single bit error. PRBS error counter register to accumulate errors. FEATURES Supports Local, Remote and Digital Loop-backs. RECEIVER: Single 3.3 V 5% power supply. On chip Clock and Data Recovery circuit for high 5 V Tolerant I/O. input jitter tolerance. Maximum Power Dissipation 1.5W. Meets the jitter tolerance requirements as specified in ITU-T G.823 1993 for E3 and Telcordia GR-499- Available in 176 pin LQFP package CORE for DS3 applications. - 40C to 85C Industrial Temperature Range. Detects and Clears LOS as per G.775. APPLICATIONS Receiver Monitor mode handles up to 20 dB flat loss with 6 dB cable attenuation. E3/DS3 Access Equipment. On chip B3ZS/HDB3 encoder and decoder that can STS1-SPE to DS3 Mapper. either be enabled or disabled. DSLAMs. On-chip clock synthesizer generates the Digital Cross Connect Systems. appropriate rate clock from a single frequency XTAL. CSU/DSU Equipment. Routers. Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com XRT75L04 FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.4 FIGURE 1. BLOCK DIAGRAM OF THE XRT 75L04 SDI CLKOUT XRT75L04 SDO XRT75L04 Serial E3Clk,DS3Clk, INT STS-1Clk Processor SClk Interface RLOL (n) CS RxON RESET RxClkINV Clock HOST/HW Invert RxClk (n) Synthesizer Peak Detector STS-1/DS3 (n) E3 (n) HDB3/ RPOS (n) REQEN (n) Clock & Data Jitter Slicer AGC/ MUX B3ZS RNEG (n)/ RTIP (n) Recovery Attenuator Decoder Equalizer LCV (n) RRing (n) LOS SR/DR Remote Detector Local LLB (n) LoopBack RLB (n) LoopBack RLOS (n) JATx/Rx TTIP (n) TPData (n) HDB3/ Line Tx Jitter B3ZS Timing MUX Driver TNData (n) Pulse Attenuator TRing (n) Encoder Control Shaping TxClk (n) TAOS (n) MTIP (n) Device MRing (n) Tx Monitor TxLEV (n) Control TxON (n) Channel 0 DMO (n) Channel 1..2 Channel 3 Notes: 1. (n) = 0, 1, 2 or 3 for respective Channels 2. Serial Processor Interface input pins are shared by the four Channels inHos Mode and redefined in theHardwar Mode. TRANSMIT INTERFACE CHARACTERISTICS Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the line Integrated Pulse Shaping Circuit. Built-in B3ZS/HDB3 Encoder (which can be disabled). Accepts Transmit Clock with duty cycle of 30%-70%. Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications. Generates pulses that comply with the DSX-3 pulse template, as specified in Telcordia GR-499-CORE and ANSI T1.102 1993. Generates pulses that comply with the STSX-1 pulse template, as specified in Telcordia GR-253-CORE. Transmitters can be turned off to support redundancy designs. RECEIVE INTERFACE CHARACTERISTICS Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery. Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications. Meets Jitter Tolerance Requirements, as specified in ITU-T G.823 1993 for E3 Applications. Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms. Built-in B3ZS/HDB3 Decoder (which can be disabled). Recovered Data can be muted while the LOS Condition is declared. 2