74HC377PW.112 Nexperia

The 74HC377PW.112 is a high-speed CMOS 8-bit latch designed using advanced depletion-load IEEE/IEC logic cells. It is designed to be compatible with industry-standard CMOS and TTL logic families. The control inputs, common to all 8 latches, are designated as INH (inhibit) and PRE (preset), while the individual latch enable inputs are denoted as EL. The state of each latch is determined by the logic level at their respective inputs and the logic level at the INH and PRE inputs. Outputs QA-QH are non-inverted, while outputs QB-QH are complementary inverted outputs. This product supports the 5 V CMOS logic level. The 74HC377PW.112 is packaged in a 12-pin PW package.