74HC377PW,112

74HC377 74HCT377 Octal D-type flip-flop with data enable positive-edge trigger Rev. 5 25 February 2021 Product data sheet 1. General description The 74HC377 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. Input E must be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V . CC 2. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Common clock and master reset Eight positive edge-triggered D-type flip-flops Input levels: For 74HC377: CMOS level For 74HCT377: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V. Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC377D -40 C to +85 C SO20 plastic small outline package 20 leads body width 7.5 mm SOT163-1 74HCT377D 74HC377PW -40 C to +85 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74HCT377PWNexperia 74HC377 74HCT377 Octal D-type flip-flop with data enable positive-edge trigger 4. Functional diagram 3 D0 Q0 2 4 D1 Q1 5 7 D2 Q2 6 8 D3 FF1 Q3 9 to OUTPUTS 13 D4 Q4 12 FF8 14 D5 Q5 15 17 D6 Q6 16 18 D7 Q7 19 1 E 11 CP mna606 Fig. 1. Functional diagram 11 1C2 1 G1 11 3 2 CP 2D 3 2 D0 Q0 4 5 4 5 D1 Q1 7 6 7 6 D2 Q2 8 9 8 9 D3 Q3 13 12 13 12 D4 Q4 14 15 D5 Q5 14 15 17 16 D6 Q6 17 16 18 19 D7 Q7 18 19 E 1 mna918 mna919 Fig. 2. Logic symbol Fig. 3. IEC logic symbol D0 D1 D2 D3 D4 D5 D6 D7 E D Q D Q D Q D Q D Q D Q D Q D Q CP CP CP CP CP CP CP CP FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 CP Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna610 Fig. 4. Logic diagram 74HC HCT377 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 25 February 2021 2 / 15