EC36 Series REGULATORY COMPLIANCE 2011/65 + 191 SVHC 2015/863 ITEM DESCRIPTION Quartz Crystal Clock Oscillators XO (SPXO) LVCMOS (CMOS) 3.3Vdc 4 Pad 3.2mm x 5.0mm Ceramic Surface Mount (SMD) ELECTRICAL SPECIFICATIONS Nominal Frequency 1MHz to 170MHz Frequency Tolerance/Stability Inclusive of all conditions: Calibration Tolerance at 25C, Frequency Stability over the Operating Temperature Range, Supply Voltage Change, Output Load Change, First Year Aging at 25C, Shock, and Vibration 100ppm Maximum 20ppm Maximum 25ppm Maximum 50ppm Maximum Operating Temperature Range -10C to +70C -40C to +85C Supply Voltage 3.3Vdc 10% Input Current 8mA Maximum over Nominal Frequency of 1MHz to 9.999999MHz 10mA Maximum over Nominal Frequency of 10MHz to 34.999999MHz 25mA Maximum over Nominal Frequency of 35MHz to 49.999999MHz 35mA Maximum over Nominal Frequency of 50MHz to 70MHz 40mA Maximum over Nominal Frequency of 70.000001MHz to 125MHz 50mA Maximum over Nominal Frequency of 125.000001MHz to 170MHz Output Voltage Logic High (V ) IOH = -4mA Oh 90% of Vdd Minimum Output Voltage Logic Low (V ) IOL = +4mA Ol 10% of Vdd Maximum Rise/Fall Time Measured at 20% to 80% of waveform 6nSec Maximum over Nominal Frequency of 1MHz to 39.999999MHz 4nSec Maximum over Nominal Frequency of 40MHz to 79.999999MHz 3nSec Maximum over Nominal Frequency of 80MHz to 100MHz 2nSec Maximum over Nominal Frequency of 100.000001MHz to 170MHz Duty Cycle Measured at 50% of waveform 50 10(%) 50 5(%) Load Drive Capability 15pF Maximum Output Logic Type CMOS Pin 1 Connection Tri-State (High Impedance) Tri-State Input Voltage (Vih and Vil) 90% of Vdd Minimum or No Connect to Enable Output, 10% of Vdd Maximum to Disable Output (High Impedance) Standby Current Disabled Output: High Impedance 10A Maximum RMS Phase Jitter 12kHz to 20MHz offset frequency 1pSec Maximum Start Up Time 10mSec Maximum Storage Temperature Range -55C to +125C Revised J: 12/7/2018 Page 2 of 12 www.ecliptek.com EC36 Series PART NUMBERING GUIDE Revised J: 12/7/2018 Page 3 of 12 www.ecliptek.com