Product Information

AS4C4M32S-7BCN

AS4C4M32S-7BCN electronic component of Alliance Memory

Datasheet
Alliance Memory DRAM 128Mb, 3.3V, 143Mhz 4M x 32 SDRAM
Manufacturer: Alliance Memory
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 7.689 ea
Line Total: USD 7.69

763 - Global Stock
Ships to you between
Wed. 29 May to Fri. 31 May
MOQ: 1  Multiples: 1
Pack Size: 1

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26 - WHS 1


Ships to you between Wed. 29 May to Fri. 31 May

MOQ : 1
Multiples : 1

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AS4C4M32S-7BCN
Alliance Memory

1 : USD 5.1613
10 : USD 4.6155
100 : USD 4.5562
190 : USD 3.9748
570 : USD 3.9274
2660 : USD 3.868
5130 : USD 3.7612
10070 : USD 3.7375

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Additional Infomation About Product

AS4C4M32S Revision History AS4C4M32S- 90 Ball TFBGA PACKAGE Revision Details Date Rev 1.0 Preliminary datasheet February 2013 Rev 2.0 Added 166MHz option -6 clock cycle time February 2013 Rev 3.0 May 2014 Add part number system Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice.AS4C4M32S 4M x 32 bit Synchronous DRAM (SDRAM) Confidential Advanced (Rev.3.0, May. /2014) Features Overview Fast access time from clock: 5.4/5.4 ns The 128Mb AS4C4M32S SDRAM is a high- speed CMOS synchronous DRAM containing 128 Fast clock rate: 166/143 MHz Mbits. It is internally configured as a quad 1M x 32 Fully synchronous operation DRAM with a synchronous interface (all signals are Internal pipelined architecture registered on the positive edge of the clock signal, Four internal banks (1M x 32-bit x 4bank) CLK). Each of the 1M x 32 bit banks is organized as Programmable Mode 4096 rows by 256 columns by 32 bits. Read and - CAS Latency: 2 or 3 write accesses to the SDRAM are burst oriented - Burst Length: 1, 2, 4, 8, or full page accesses start at a selected location and continue for a programmed number of locations in a - Burst Type: Sequential & Interleaved programmed sequence. Accesses begin with the - Burst-Read-Single-Write registration of a BankActivate command which is Burst stop function then followed by a Read or Write command. Individual byte controlled by DQM0-3 The SDRAM provides for programmable Read Auto Refresh and Self Refresh or Write burst lengths of 1, 2, 4, 8, or full page, with Operating temperature range a burst termination option. An auto precharge - Commercial (0 ~ 70C) function may be enabled to provide a self-timed row - Industrial (-40 ~ 85C) precharge that is initiated at the end of the burst 4096 refresh cycles/64ms sequence. The refresh functions, either Auto or Self Refresh are easy to use. Single 3.3V 0.3V. power supply By having a programmable mode register, the Interface: LVTTL system can choose the most suitable modes to 90-ball 8 x 13 x 1.2mm TFBGA package maximize its performance. These devices are well - Pb and Halogen Free suited for applications requiring high memory bandwidth. Table 1. Key Specifications AS4C4M32S -6/7 Clock Cycle time(min.) 6/7 ns tCK3 tAC3 Access time from CLK (max.) 5.4/5.4 ns tRAS Row Active time(min.) 42/42 ns tRC 60/63 ns Row Cycle time(min.) Table 2.Ordering Information Part Number Frequency Package Temperature Temp Range AS4C4M32S-6BIN 166MHz 90-ball TFBGA Industrial -40 ~ 85C AS4C4M32S-7BCN 143MHz 90-ball TFBGA Commercial 0 ~ 70C B: indicates 90-ball (8.0 x 13 x 1.4mm) TFBGA package N: indicates Pb and Halogen Free ROHS Alliance Memory Confidential 1 Rev. 3.0 May. /2014

HS Compliance

Tariff Desc

8542.32.00 -- Memories
               Monolithic integrated circuits:

Alliance Memory may also be referenced as

ACM
ALLIANCE MEMORY, INC.
ALLIANCE SEMI

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