Product Information

AD5764SSUZ-EP-RL7

AD5764SSUZ-EP-RL7 electronic component of Analog Devices

Datasheet
Digital to Analog Converters - DAC DAC, Quad 16bit 15V

Manufacturer: Analog Devices
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500: USD 66.9859 ea
Line Total: USD 33492.95

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MOQ: 500  Multiples: 500
Pack Size: 500
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AD5764SSUZ-EP-RL7
Analog Devices

1 : USD 106.9853

0 - WHS 2


Ships to you between Tue. 21 May to Mon. 27 May

MOQ : 1
Multiples : 1

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AD5764SSUZ-EP-RL7
Analog Devices

1 : USD 106.9853

0 - WHS 3


Ships to you between Tue. 21 May to Mon. 27 May

MOQ : 500
Multiples : 500

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AD5764SSUZ-EP-RL7
Analog Devices

500 : USD 120.4797

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Ships to you between Mon. 27 May to Wed. 29 May

MOQ : 500
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AD5764SSUZ-EP-RL7
Analog Devices

500 : USD 66.9859

     
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Complete Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC Data Sheet AD5764 FEATURES GENERAL DESCRIPTION Complete quad, 16-bit digital-to-analog The AD5764 is a quad, 16-bit, serial input, bipolar voltage converter (DAC) output DAC that operates from supply voltages of 11.4 V to Programmable output range 16.5 V. Nominal full-scale output range is 10 V. The AD5764 10 V, 10.2564 V, or 10.5263 V provides integrated output amplifiers, reference buffers, and 1 LSB maximum INL error, 1 LSB maximum DNL error proprietary power-up/power-down control circuitry. The part Low noise: 60 nV/Hz also features a digital I/O port that is programmed via the serial Settling time: 10 s maximum interface. The part incorporates digital offset and gain adjust Integrated reference buffers registers per channel. Output control during power-up/brownout The AD5764 is a high performance converter that offers guar- Programmable short-circuit protection anteed monotonicity, integral nonlinearity (INL) of 1 LSB, low Simultaneous updating via LDAC noise, and 10 s settling time. During power-up (when the CLR Asynchronous to zero code supply voltages are changing), VOUTx is clamped to 0 V via a Digital offset and gain adjust low impedance path. Logic output control pins The AD5764 uses a serial interface that operates at clock rates of DSP-/microcontroller-compatible serial interface up to 30 MHz and is compatible with DSP and microcontroller Temperature range: 40C to +85C 1 interface standards. Double buffering allows the simultaneous iCMOS process technology updating of all DACs. The input coding is programmable to APPLICATIONS either twos complement or offset binary formats. The asynchro- nous clear function clears the data register to either bipolar zero or Industrial automation zero scale depending on the coding used. The AD5764 is ideal Open-loop/closed-loop servo control for both closed-loop servo control and open-loop control appli- Process control cations. The AD5764 is available in a 32-lead TQFP, and offers Data acquisition systems guaranteed specifications over the 40C to +85C industrial Automatic test equipment temperature range. See Figure 1 for the functional block diagram. Automotive test and measurement High accuracy instrumentation Table 1. Related Devices Part No. Description AD5764R AD5764 with internal voltage reference AD5744R Complete quad, 14-bit, high accuracy, serial input, bipolar voltage output DAC with internal voltage reference 1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher voltage levels, iCMOS is a technology platform that enables the development of analog ICs capable of 30 V and operating at 15 V supplies, allowing dramatic reductions in power consumption and package size, and increased ac and dc performance. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20062011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AD5764 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Function Register ....................................................................... 21 Applications....................................................................................... 1 Data Register............................................................................... 21 General Description ......................................................................... 1 Coarse Gain Register ................................................................. 21 Revision History ............................................................................... 2 Fine Gain Register...................................................................... 22 Functional Block Diagram .............................................................. 3 Offset Register ............................................................................ 22 Specifications..................................................................................... 4 Offset and Gain Adjustment Worked Example...................... 23 AC Performance Characteristics ................................................ 5 Design Features............................................................................... 24 Timing Characteristics ................................................................ 6 Analog Output Control ............................................................. 24 Absolute Maximum Ratings............................................................ 9 Digital Offset and Gain Control............................................... 24 ESD Caution.................................................................................. 9 Programmable Short-Circuit Protection ................................ 24 Pin Configuration and Function Descriptions........................... 10 Digital I/O Port........................................................................... 24 Typical Performance Characteristics ........................................... 12 Local Ground Offset Adjust...................................................... 24 Terminology .................................................................................... 17 Applications Information .............................................................. 25 Theory of Operation ...................................................................... 18 Typical Operating Circuit ......................................................... 25 DAC Architecture....................................................................... 18 Layout Guidelines........................................................................... 27 Reference Buffers........................................................................ 18 Galvanically Isolated Interface ................................................. 27 Serial Interface ............................................................................ 18 Microprocessor Interfacing....................................................... 27 Simultaneous Updating via LDAC........................................... 19 Evaluation Board........................................................................ 27 Outline Dimensions....................................................................... 28 Transfer Function ....................................................................... 20 Ordering Guide .......................................................................... 28 CLR Asynchronous Clear ( )....................................................... 20 REVISION HISTORY 9/11Rev. E to Rev. F Changes to Table 20 ....................................................................... 26 Changed 30 MHz to 50 MHz Throughout.................................... 1 Deleted AD5764 to MC68HC11 Interface Section.................... 27 Changes to t , t , and t Parameters, Table 4.................................. 6 Deleted Figure 38 Renumbered Sequentially ............................ 27 1 2 3 Deleted AD5764 to 8XC51 Interface Section, Figure 39, 7/11Rev. D to Rev. E AD5764 to ADSP-2101 Interface Section, Figure 40, and Changed 30 MHz to 50 MHz Throughout.................................... 1 AD5764 to PIC16C6x/PIC16C7x Interface Section .................. 28 Changes to t1, t2, and t3 Parameters, Table 4.................................. 6 04/08Rev. A to Rev. B 8/09Rev. C to Rev. D Changes to Table Summary Statement, Specifications Section...4 Changes to Table 2 and Table 3 Endnotes ..................................... 6 Changes to Power Requirements Parameter, Table 2 and Changes to t6 Parameter and Endnotes, Table 4........................... 7 Table Summary Statement................................................................5 1/09Rev. B to Rev. C Changes to t Parameter, Table 4 ....................................................6 16 Changes to General Description Section ...................................... 1 Changes to Table 6.......................................................................... 10 Changes to Figure 1.......................................................................... 3 Changed VSS/VDD to AVSS/AVDD in Typical Performance Changes to Table 2 Conditions ....................................................... 4 Characteristics Section .................................................................. 13 Changes to Table 3 Conditions ....................................................... 5 Changes to Table 16 ....................................................................... 22 Changes to Table 4 Conditions ....................................................... 6 Changes to Table 18 ....................................................................... 23 Changes to Figure 5.......................................................................... 8 Changes to Typical Operating Circuit Section........................... 28 Changes to Table 5............................................................................ 9 Changes to AD5764 to ADSP-2101 Section ............................... 29 Changes to Table 6.......................................................................... 10 Changes to Ordering Guide .......................................................... 30 Changes to Figure 34...................................................................... 19 1/07Rev. 0 to Rev. A Changes to Table 7 and Table 10................................................... 20 Changes to Absolute Maximum Ratings..................................... 10 Added Table 8 Renumbered Sequentially .................................. 20 Changes to Figure 25 and Figure 26............................................. 16 Changes to Table 11 and Table 12 ................................................ 21 Changes to Digital Offset and Gain Control Section ................ 24 3/06Revision 0: Initial Version Rev. F Page 2 of 28

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