Differential Input, 555 kSPS 12-Bit ADC in an 8-Lead SOT-23 Data Sheet AD7452 FEATURES FUNCTIONAL BLOCK DIAGRAM V Specified for V of 3 V and 5 V DD DD Low power at max throughput rate 3.3 mW max at 555 kSPS with 3 V supplies 7.25 mW max at 555 kSPS with 5 V supplies Fully differential analog input V IN+ 12-BIT T/H SUCCESSIVE Wide input bandwidth V APPROXIMATION IN ADC 70 dB SINAD at 100 kHz input frequency V REF Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI/QSPI/MICROWIRE/DSP compatible SCLK Power-down mode: 1 A max SDATA AD7452 CONTROL LOGIC 8-lead SOT-23 package CS APPLICATIONS Transducer interface Battery-powered systems GND Data acquisition systems Figure 1. Portable instrumentation Motor control The SAR architecture of this part ensures that there are no pipeline delays. GENERAL DESCRIPTION The AD7452 uses advanced design techniques to achieve very 1 low power dissipation. The AD7452 is a 12-bit, high speed, low power, successive approximation (SAR) analog-to-digital converter that features a PRODUCT HIGHLIGHTS fully differential analog input. This part operates from a single 1. Operation with Either 3 V or 5 V Power Supplies. 3 V or 5 V power supply and features throughput rates up to 2. High Throughput with Low Power Consumption. With a 555 kSPS. 3 V supply, the AD7452 offers 3.3 mW max power consumption for 555 kSPS throughput. The part contains a low noise, wide bandwidth, differential 3. Fully Differential Analog Input. track-and-hold amplifier (T/H) that can handle input 4. Flexible Power/Serial Clock Speed Management. The frequencies up to 3.5 MHz. The reference voltage is applied conversion rate is determined by the serial clock, allowing externally to the VREF pin and can be varied from 100 mV to the power to be reduced as the conversion time is reduced 3.5 V depending on the power supply and what suits the through the serial clock speed increase. This part also application. The value of the reference voltage determines the features a shutdown mode to maximize power efficiency at common-mode voltage range of the part. With this truly lower throughput rates. differential input structure and variable reference input, the 5. Variable Voltage Reference Input. user can select a variety of input ranges and bias points. 6. No Pipeline Delay. The conversion process and data acquisition are controlled 7. Accurate Control of the Sampling Instant via a CS Input using CS and the serial clock, allowing the device to interface and Once-Off Conversion Control. with microprocessors or DSPs. The input signals are sampled 8. ENOB > 8 Bits Typically with 100 mV Reference. on the falling edge of CS, and the conversion is also initiated at this point. 1 Protected by U.S. Patent Number 6,681,332. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20032015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 03154-A-001AD7452 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Connection Diagram ................................................... 14 Applications ....................................................................................... 1 Analog Input ............................................................................... 14 General Description ......................................................................... 1 Driving Differential Inputs ....................................................... 16 Functional Block Diagram .............................................................. 1 Digital Inputs .............................................................................. 18 Product Highlights ........................................................................... 1 Reference ..................................................................................... 18 Revision History ............................................................................... 2 Single-Ended Operation ............................................................ 18 Specif icat ions ..................................................................................... 3 Serial Interface ............................................................................ 19 Timing Specifications .................................................................. 5 Modes of Operation ....................................................................... 20 Absolute Maximum Ratings ............................................................ 6 Normal Mode .............................................................................. 20 ESD Caution .................................................................................. 6 Power-Down Mode .................................................................... 20 Pin Configuration and Function Descriptions ............................. 7 Power-Up Time .......................................................................... 21 Terminology ...................................................................................... 8 Power vs. Throughput Rate ....................................................... 22 Typical Performance Characteristics ........................................... 10 Application Hints ....................................................................... 22 Circuit Information ........................................................................ 13 Evaluating the AD7452s Performance .................................... 23 Converter Operation .................................................................. 13 Outline Dimensions ....................................................................... 24 ADC Transfer Function ............................................................. 13 Ordering Guide .......................................................................... 24 REVISION HISTORY 7/15Rev. B to Rev. C 2/04Rev. A to Rev. B Changed F to f .................................................... Throughout Added Patent Note ............................................................................ 1 SCLK SCLK Changes to Figure 29 ...................................................................... 16 Changes to Power vs. Throughput Rate Section ........................ 22 2/04Rev. 0 to Rev. A Deleted Microprocessor and DSP Interfacing Section and Updated Formatting ........................................................... Universal AD7452 to ADSP-21xx Section .................................................... 22 Changes to Applications section ..................................................... 1 Deleted Figure 40, Figure 41, and Figure 42 Renumbered Changes to General Description ..................................................... 1 Sequentially ..................................................................................... 23 Changes to Specifications ................................................................. 4 Deleted AD7452 to TMS320C5x/C54x Section and AD7452 to Changes to Timing Specifications ................................................... 5 Changes to Timing Example ......................................................... 19 DSP56xxx Section ........................................................................... 23 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 9/03Revision 0: Initial Version Rev. C Page 2 of 24