Complete 12-Bit, 25 MSPS Monolithic A/D Converter AD9225 FEATURES FUNCTIONAL BLOCK DIAGRAM Monolithic 12-Bit, 25 MSPS ADC CLK AVDD DRVDD Low Power Dissipation: 280 mW Single 5 V Supply SHA VINA MDAC1 MDAC2 MDAC3 No Missing Codes Guaranteed GAIN = 16 GAIN = 4 GAIN = 4 VINB Differential Nonlinearity Error: 0.4 LSB 5 3 3 ADC ADC ADC ADC Complete On-Chip Sample-and-Hold Amplifier and CAPT 5 3 3 4 Voltage Reference CAPB DIGITAL CORRECTION LOGIC Signal-to-Noise and Distortion Ratio: 71 dB 12 VREF Spurious-Free Dynamic Range: 85 dB OUTPUT BUFFERS OTR SENSE Out-of-Range Indicator BIT 1 (MSB) 1V MODE Straight Binary Output Data BIT 12 SELECT AD9225 28-Lead SOIC (LSB) 28-Lead SSOP REFCOM AVSS CML DRVSS Compatible with 3 V Logic A single clock input is used to control all internal conversion GENERAL DESCRIPTION cycles. The digital output data is presented in straight binary The AD9225 is a monolithic, single-supply, 12-bit, 25 MSPS output format. An out-of-range signal indicates an overflow analog-to-digital converter with an on-chip, high performance condition that can be used with the most significant bit to deter- sample-and-hold amplifier and voltage reference. The AD9225 mine low or high overflow. uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 25 MSPS PRODUCT HIGHLIGHTS data rates, and guarantees no missing codes over the full operat- The AD9225 is fabricated on a very cost effective CMOS pro- ing temperature range. cess. High speed precision analog circuits are combined with The AD9225 combines a low cost, high speed CMOS process high density logic circuits. and a novel architecture to achieve the resolution and speed of The AD9225 offers a complete, single-chip sampling, 12-bit, existing bipolar implementations at a fraction of the power 25 MSPS analog-to-digital conversion function in 28-lead consumption and cost. SOIC and SSOP packages. The input of the AD9225 allows for easy interfacing to both Low PowerThe AD9225 at 280 mW consumes a fraction of imaging and communications systems. With the devices truly the power presently available in monolithic solutions. differential input structure, the user can select a variety of input ranges and offsets, including single-ended applications. The On-Board Sample-and-Hold Amplifier (SHA)The versa- dynamic performance is excellent. tile SHA input can be configured for either single-ended or differential inputs. The sample-and-hold amplifier (SHA) is well suited for both multiplexed systems that switch full-scale voltage levels in succes- Out-of-Range (OTR)The OTR output bit indicates when sive channels and sampling single-channel inputs at frequencies the input signal is beyond the AD9225s input range. up to and well beyond the Nyquist rate. Single SupplyThe AD9225 uses a single 5 V power supply, The AD9225s wideband input, combined with the power and simplifying system power supply design. It also features a sepa- cost savings over previously available monolithics, suits applica- rate digital driven supply line to accommodate 3 V and 5 V logic tions in communications, imaging, and medical ultrasound. families. The AD9225 has an on-board programmable reference. An Pin CompatibilityThe AD9225 is pin compatible with the external reference can also be chosen to suit the dc accuracy AD9220, AD9221, AD9223, and AD9224 ADCs. and temperature drift requirements of an application. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners. 781/461-3113AD9225SPECIFICATIONS (AVDD = 5 V, DRVDD = 5 V, f = 25 MSPS, VREF = 2.0 V, VINB = 2.5 V dc, T to T , SAMPLE MIN MAX DC SPECIFICATIONS unless otherwise noted.) Parameter Min Typ Max Unit RESOLUTION 12 Bits MAX CONVERSION RATE 25 MHz INPUT REFERRED NOISE VREF = 1.0 V 0.35 LSB rms VREF = 2.0 V 0.17 LSB rms ACCURACY Integral Nonlinearity (INL) 1.0 2.5 LSB Differential Nonlinearity (DNL) 0.4 1.0 LSB No Missing Codes 12 Bits Guaranteed Zero Error ( 25C) 0.3 0.6 % FSR 1 Gain Error ( 25C) 0.5 2.2 % FSR 2 Gain Error ( 25C) 0.4 1.7 % FSR TEMPERATURE DRIFT Zero Error 2 ppm/ C 1 Gain Error 26 ppm/ C 2 Gain Error 0.4 ppm/ C POWER SUPPLY REJECTION AVDD (+5 V 0.25 V) 0.1 0.35 % FSR ANALOG INPUT Input Span 2 V p-p 4V p-p Input (VINA or VINB) Range 0 V AVDD V Input Capacitance 10 pF INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) 1.0 V Output Voltage Tolerance (1 V Mode) 5 17 mV Output Voltage (2.0 V Mode) 2.0 V Output Voltage Tolerance (2.0 V Mode) 10 35 mV Output Current (Available for External Loads) 1.0 mA 3 Load Regulation 1.0 3.4 mV REFERENCE INPUT RESISTANCE 8 kW POWER SUPPLIES Supply Voltages AVDD 4.75 5 5.25 V (5% AVDD Operating) DRVDD 2.85 5.25 V (5% DRVDD Operating) Supply Currents IAVDD 65 72.5 mA IDRVDD 2.0 4.0 mA POWER CONSUMPTION External Reference 280 310 mW (VREF = 1 V) 335 373 mW (VREF = 2 V) Internal Reference 290 mW (VREF = 1 V) 345 mW (VREF = 2 V) NOTES 1 Includes internal voltage reference error. 2 Excludes internal voltage reference error. 3 Load regulation with 1 mA load current (in addition to that required by the AD9225). Specifications subject to change without notice. 2 Rev. C