6-Output Clock Generator with Integrated 2.2 GHz VCO Data Sheet AD9518-2 FEATURES FUNCTIONAL BLOCK DIAGRAM CP LF Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 2.05 GHz to 2.33 GHz External VCO/VCXO to 2.4 GHz optional REF1 STATUS MONITOR 1 differential or 2 single-ended reference inputs REFIN Reference monitoring capability VCO REF2 Automatic revertive and manual reference switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz DIVIDER CLK AND MUXs Programmable delays in path to PFD Digital or analog lock detect, selectable OUT0 DIV/ LVPECL 3 pairs of 1.6 GHz LVPECL outputs OUT1 OUT2 Each output pair shares a 1-to-32 divider with coarse DIV/ LVPECL OUT3 phase delay OUT4 DIV/ LVPECL OUT5 Additive output jitter: 225 fs rms SERIAL CONTROL PORT Channel-to-channel skew paired outputs of <10 ps AND AD9518-2 DIGITAL LOGIC Automatic synchronization of all outputs on power-up Manual output synchronization available Figure 1. Available in a 48-lead LFCSP APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation GENERAL DESCRIPTION 1 In addition, the AD9516 and AD9517 are similar to the AD9518 The AD9518-2 provides a multi-output clock distribution but have a different combination of outputs. function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.05 GHz Each pair of outputs has dividers that allow both the divide to 2.33 GHz. Optionally, an external VCO/VCXO of up to ratio and coarse delay (or phase) to be set. The range of division 2.4 GHz can be used. for the LVPECL outputs is 1 to 32. The AD9518-2 emphasizes low jitter and phase noise to The AD9518-2 is available in a 48-lead LFCSP and can be maximize data converter performance, and it can benefit other operated from a single 3.3 V supply. An external VCO, which applications with demanding phase noise and jitter requirements. requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate The AD9518-2 features six LVPECL outputs (in three pairs). LVPECL power supply can be from 2.5 V to 3.3 V (nominal). The LVPECL outputs operate to 1.6 GHz. The AD9518-2 is specified for operation over the industrial For applications that require additional outputs, a crystal range of 40C to +85C. reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. 1 AD9518 is used throughout the data sheet to refer to all the members of the AD9518 family. However, when AD9518-2 is used, it refers to that specific member of the AD9518 family. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 20072012 Analog Devices, Inc. All rights reserved. SWITCHOVER AND MONITOR PLL 06431-001AD9518-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .................................................................... 13 Applications ....................................................................................... 1 ESD Caution................................................................................ 13 General Description ......................................................................... 1 Pin Configuration and Function Descriptions ........................... 14 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ........................................... 16 Revision History ............................................................................... 3 Terminology .................................................................................... 20 Specifications ..................................................................................... 4 Detailed Block Diagram ................................................................ 21 Power Supply Requirements ....................................................... 4 Theory of Operation ...................................................................... 22 PLL Characteristics ...................................................................... 4 Operational Configurations ...................................................... 22 Clock Inputs .................................................................................. 6 Digital Lock Detect (DLD) ....................................................... 30 Clock Outputs ............................................................................... 6 Clock Distribution ..................................................................... 34 Timing Characteristics ................................................................ 6 Reset Modes ................................................................................ 38 Clock Output Additive Phase Noise (Distribution Only Power-Down Modes .................................................................. 38 VCO Divider Not Used) .............................................................. 7 Serial Control Port ......................................................................... 40 Clock Output Absolute Phase Noise (Internal VCO Used) .... 7 Serial Control Port Pin Descriptions ....................................... 40 Clock Output Absolute Time Jitter (Clock Generation General Operation of Serial Control Port ............................... 40 Using Internal VCO) .................................................................... 8 The Instruction Word (16 Bits) ................................................ 41 Clock Output Absolute Time Jitter (Clock Cleanup Using MSB/LSB First Transfers ........................................................... 41 Internal VCO) ............................................................................... 8 Thermal Performance .................................................................... 44 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO) ................................................................ 8 Control Registers ............................................................................ 45 Clock Output Additive Time Jitter (VCO Divider Control Register Map Overview .............................................. 45 Not Used) ....................................................................................... 9 Control Register Map Descriptions ......................................... 47 Clock Output Additive Time Jitter (VCO Divider Used) ....... 9 Applications Information .............................................................. 59 Serial Control Port ..................................................................... 10 Frequency Planning Using the AD9518 .................................. 59 PD, SYNC, and RESET Pins ..................................................... 10 Using the AD9518 Outputs for ADC Clock Applications .... 59 LD, STATUS, and REFMON Pins ............................................ 11 LVPECL Clock Distribution ..................................................... 60 Power Dissipation ....................................................................... 11 Outline Dimensions ....................................................................... 61 Timing Diagrams ............................................................................ 12 Ordering Guide .......................................................................... 61 Absolute Maximum Ratings .......................................................... 13 Rev. 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