ICS9250 -10 Frequency Timing Generator for Pentium II Systems General Description Features ( ) )) %& ( %& ) ( 7 ) * +,-. ( %& +( 7 ( 3 3 7 ) ( / ) 0 %& +( 7 ( ( 7 8 ) 3 /74 74 )1. ) 0 2 %& ( 8 ) A 3 7 % 3 0 %& 7 7 ) +* +4 0 5/ %& 6 ( 7 ( -89 05 / %& ( ( ( 7 ( 7 : + (( ( 7 ( 7 ( ( 7 ( 7 7 ( 7 < ( :) (( ( : 8 ( ,= : > 5 / %& Block Diagram Pin Configuration 56-Pin 300 mil SSOP I G ( ( ,, 7 7 ( Power Groups ,, 6, B -89 C , 6 B E ,, 6, B ) FGD2 E ,, 6, B FF ,,5 6,5 B 5/ %& E ,, 6, B +,-. H9 +,-. D2 E ,,F 6,F B FG D E Pentium II is a trademark of Intel Corporation 2 I C is a trademark of Philips Corporation ,, 6, B )1. ) E 9250-10 Rev K 12/14/01 ICS9250 - 10 Pin Descriptions PEIN NUMBERPEIN NAMTNYP DESCRIPTIO Latched input at Power On. this determines the IOAPIC frequency. When a0 is latched, IOAPIC Freq=16.67MHz FNREQ APIC I When1 is latched, IOAPIC Freq=33.3MHz 1 This pin has a 60K internal pull-up. RTEF0O.U 3.3V, 14.318MHz reference clock output Crystal input, has internal load cap (33pF) and feedback 31XNI resistor from X2 Crystal output, nominally 14.318MHz. Has internal load 42XTOU cap (33pF) 5, 6, 14, 17, 23, GRND (0:5)PyW Ground pins for 3.3V suppl 24, 35, 41, 47 8 , 73TV66 1:0OBU 3.3V Fixed 66MHz clock outputs for HU 2, 9, 10, 21, VRDD (0:5)PyW 3.3V power suppl 22, 27, 33, 38, 44 20,19,18,16, PTCICLK 7:0 OSU 3.3V PCI clock outputs, with Synchronous CPUCLK 15,13,12,11 2)5, 264T8MHz (0:1OBU 3.3V Fixed 48MHz clock outputs for US Function Select pins. Determines CPU frequency, all output 2)8, 29FNS (0:1 I functionality. Please refer to Functionality table on page 3. 2 3A0SNDAT IIData input for C serial input. 2 3K1SNCL IIClock input of C input Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the 3 2PND I VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 36, 37, 39, 40, 42, 3.3V output running 100MHz. All SDRAM outputs can be turned STDRAM 7:0 OU 2 off through I C 43, 45, 46 2 3F4STDRAM OIU 3.3V free running 100MHz SDRAM not affected by C 5 6,48GRNDL 1:0PCW Ground for 2.5V power supply for CPU & API 2.5V Host bus clock output. 66MHz or 100MHz depending on FS 4 9,50,52CTPUCLK 2:0 OU (0:1) pins Refer page 3. 5)1, 53VRDDL (0:1PCW 2.5V power suypply for CPU & IOAPI 5 4, 55ITOAPIC 1:0O.U 2.5V clock outputs running at 16.67MHz or 33.3MHz