14-Bit, 2.5 GSPS, RF Digital-to-Analog Converter Data Sheet AD9739 FEATURES FUNCTIONAL BLOCK DIAGRAM RESET IRQ Direct RF synthesis at 2.5 GSPS update rate DC to 1.25 GHz in baseband mode AD9739 1.25 GHz to 3.0 GHz in mix mode 1.2V SDIO SDO Industry leading single/multicarrier IF or RF synthesis SPI DAC BIAS CS VREF f = 350 MHz, ACLR =80 dBc OUT SCLK I120 f = 950 MHz, ACLR = 78 dBc OUT f = 2100 MHz, ACLR = 69 dBc OUT Dual-port LVDS data interface Up to 1.25 GSPS operation IOUTP Source synchronous DDR clocking TxDAC DCI CORE IOUTN Pin-compatible with the AD9739A Multichip synchronization capability Programmable output current: 8.7 mA to 31.7 mA Low power: 1.16 W at 2.5 GSPS APPLICATIONS CLK DISTRIBUTION DCO (DIV-BY-4) Broadband communications systems SYNC OUT SYNC- Military jammers SYNC IN CONTROLLER Instrumentation, automatic test equipment Radar, avionics DACCLK Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9739 is a 14-bit, 2.5 GSPS high performance RF digital- 1. Ability to synthesize high quality wideband signals with to-analog converter (DAC) capable of synthesizing wideband bandwidths of up to 1.25 GHz in the first or second signals from dc up to 3.0 GHz. Its DAC core features a quad- Nyquist zone. switch architecture that provides exceptionally low distortion 2. A proprietary quad-switch DAC architecture provides performance with an industry-leading direct RF synthesis exceptional ac linearity performance while enabling mix capability. This feature enables multicarrier generation up to mode operation. the Nyquist frequency in baseband mode as well as second and 3. A dual-port, double data rate, LVDS interface supports the third Nyquist zones in mix mode. The output current can be maximum conversion rate of 2500 MSPS. programmed over the 8.66 mA to 31.66 mA range. 4. On-chip controllers manage external and internal clock domain skews. The inclusion of on-chip controllers simplifies system integration. 5. A multichip synchronization capability. A dual-port, source synchronous, LVDS interface simplifies the 6. Programmable differential current output with an 8.66 mA digital interface with existing FGPA/ASIC technology. On-chip to 31.66 mA range. controllers are used to manage external and internal clock domain variations over temperature to ensure reliable data transfer from the host to the DAC core. Multichip synchronization is possible with an on-chip synchronization controller. A serial peripheral interface (SPI) is used for device configuration as well as readback of status registers. The AD9739 is manufactured on a 0.18 m CMOS process and operates from 1.8 V and 3.3 V supplies. It is supplied in a 160-ball chip scale ball grid array for reduced package parasitics. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20092017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. DB1 13:0 DB0 13:0 DATA CONTROLLER LVDS DDR LVDS DDR RECEIVER RECEIVER 4-TO-1 DATA ASSEMBLER DATA LATCH DLL (MU CONTROLLER) 07851-001AD9739 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DCI Phase Alignment Status .................................................... 24 Applications ....................................................................................... 1 SYNC IN Phase Alignment Status .......................................... 24 General Description ......................................................................... 1 Data Receiver Controller Configuration ................................. 24 Functional Block Diagram .............................................................. 1 Data Receiver Controller Data Sample Delay Value ............ 25 Product Highlights ........................................................................... 1 Data and Sync Receiver Controller DCI Delay Value/Window and Phase Rotation ......................................... 25 Revision History ............................................................................... 3 Data Receiver Controller Delay Line Status and Sync Specif icat ions ..................................................................................... 5 Controller SYNC OUT Status ................................................. 25 DC Specifications ......................................................................... 5 Sync and Data Receiver Controller Lock/Tracking Status .... 26 LVDS Digital Specifications ........................................................ 6 CLK Input Common Mode ...................................................... 26 Serial Port Specifications ............................................................. 7 Mu Controller Configuration and Status ................................ 26 AC Specifications .......................................................................... 8 Part ID ......................................................................................... 27 Absolute Maximum Ratings ............................................................ 9 Theory of Operation ...................................................................... 28 Thermal Resistance ...................................................................... 9 LVDS Data Port Interface .......................................................... 29 ESD Caution .................................................................................. 9 Mu Controller ............................................................................. 33 Pin Configurations and Function Descriptions ......................... 10 Interrupt Requests ...................................................................... 35 Typical Performance Characteristics ........................................... 13 Multiple Device Synchronization ............................................. 36 AC (Normal Mode) .................................................................... 13 Analog Interface Considerations .................................................. 39 AC (Mix Mode) .......................................................................... 16 Analog Modes of Operation ..................................................... 39 Terminology .................................................................................... 18 Clock Input Considerations ...................................................... 40 Serial Port Interface (SPI) Register ............................................... 19 Voltage Reference ....................................................................... 41 SPI Register Map Description ................................................... 19 Analog Outputs .......................................................................... 41 SPI Operation .............................................................................. 19 Nonideal Spectral Artifacts ....................................................... 44 SPI Register Map ............................................................................. 21 Lab Evaluation of the AD9739 ................................................. 45 SPI Port Configuration and Software Reset ............................ 23 Power Dissipation and Supply Domains ................................. 45 Power-Down LVDS Interface and TxDAC ............................ 23 Recommended Start-Up Sequence .......................................... 46 Controller Clock Disable ........................................................... 23 Outline Dimensions ....................................................................... 49 Interrupt Request (IRQ) Enable/Status ................................... 23 Ordering Guide .......................................................................... 49 TxDAC Full-Scale Current Setting (I ) and Sleep ........... 24 OUTFS TxDAC Quad-Switch Mode of Operation .............................. 24 Rev. D Page 2 of 49