Complete, High Resolution 16-Bit A/D Converter ADADC71 FUNCTIONAL BLOCK DIAGRAM FEATURES 16-bit converter with reference and clock (MSB) BIT 1 1 32 SHORT CYCLE BIT 2 2 ADADC71 31 CONVERT COMMAND 0.003% maximum nonlinearity BIT 3 3 30 +5V DC SUPPLY V REFERENCE L No missing codes to 14 bits BIT 4 4 29 GAIN ADJUST BIT 5 5 28 +15V DC SUPPLY V CC Fast conversion: 35 s (14 bit) BIT 6 6 27 COMPARATOR IN 7.5k Short cycle capability BIT 7 7 26 BIPOLAR OFFSET BIT 8 8 25 +10V Parallel logic outputs 3.75k 3.75k BIT 9 9 24 +20V Low power: 645 mW typical BIT 10 10 23 REF OUT (4.3V) BIT 11 11 22 ANALOG COMMON Industry standard pinout BIT 12 12 16-BIT SAR 21 15V DC SUPPLY V EE (LSB FOR 13 BITS) BIT 13 13 20 CLOCK OUT (LSB FOR 14 BITS) BIT 14 14 19 DIGITAL COMMON COMPARATOR CLOCK APPLICATIONS BIT 15 15 18 STATUS BIT 16 16 17 NC Medical and analytic instrumentation NC = NO CONNECT Precision measurement for industrial robots Automatic test equipment Figure 1. Multi-channel data acquisition systems Servo-control systems GENERAL DESCRIPTION PRODUCT HIGHLIGHTS 1. The ADADC71 provides 16-bit resolution with a The ADADC71 is a high resolution 16-bit hybrid IC analog-to- maximum linearity error less than 0.003% (0.006% for digital converter including reference, clock, and laser-trimmed o J grades) at 25 C. thin-film components. The package is a compact 32-pin hermetic ceramic DIP. The thin-film scaling resistors allow 2. Conversion time is 35 s typical (50 s max) to 14 bits with analog input ranges of 2.5 V, 5 V, 10 V, 0 to +5 V, 0 to +10 V, short cycle capability. and 0 to +20 V. 3. Two binary codes are available on the ADADC71 output: complementary straight binary (CSB) for unipolar input Important performance characteristics of the device are voltage ranges, and complementary offset binary (COB) for maximum linearity error of 0.003% of FSR, and maximum bipolar input ranges. Complementary twos complement conversion time of 50 s. This performance is due to innovative (CTC) coding may be obtained by inverting Pin 1 (MSB). design and the use of proprietary monolithic DAC chips. Laser- trimmed thin-film resistors provide the linearity and wide 4. The proprietary chips used in this hybrid design provide temperature range for no missing codes. excellent stability over temperature, and lower chip count for improved reliability. The ADADC71 provides data in parallel format with corresponding clock and status outputs. All digital inputs and outputs are TTL-compatible. The ADADC71 used to provide data in a serial format. The serial output function is no longer available after date code 0120. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2005 Analog Devices, Inc. All rights reserved. 16-BIT DAC 03537-001ADADC71 TABLE OF CONTENTS Specifications..................................................................................... 3 Digital Output Data ......................................................................8 Absolute Maximum Ratings............................................................ 5 Input Scaling ..................................................................................8 ESD Caution.................................................................................. 5 Calibration (14-Bit Resolution Examples).................................9 Theory of Operation ........................................................................ 6 Grounding, Decoupling, and Layout Considerations ........... 10 Description of Operation ................................................................ 7 T/H Requirements for High Resolution Applications .......... 10 Gain Adjustment .......................................................................... 7 Using the ADADC71 at Slower Conversion Times............... 11 Zero Offset Adjustment............................................................... 7 Outline Dimensions ....................................................................... 12 Timing............................................................................................ 7 Ordering Guide .......................................................................... 12 REVISION HISTORY 6/05Rev. B to Rev. C Updated Format..................................................................Universal Removed ADADC72..........................................................Universal Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 12 Rev. C Page 2 of 12