Dual 3 MHz, 600 mA Buck Regulator with 150 mA LDO ADP5022 FEATURES GENERAL DESCRIPTION Input voltage range: 2.4 V to 5.5 V The ADP5022 is a micro power management unit (micro PMU) Tiny 16-ball, 2 mm 2 mm WLCSP package that combines two high performance buck regulators and a low Overcurrent and thermal protection dropout regulator (LDO) in a tiny 16-ball 2.08 mm 2.08 mm Soft start WLCSP to meet demanding performance and board space Factory programmable undervoltage lockout on VDDA requirements. system supply of either 2.2 V or 3.9 V The high switching frequency of the buck regulators enables Factory programmable default output voltages for all tiny multilayer external components and minimizes the board 3 channels space required. When the MODE pin is set high, the buck reg- Buck1 and Buck2 key specifications ulators operate in forced PWM mode. When the MODE pin is Current mode architecture for excellent transient response set low, the buck regulators automatically switch operating 3 MHz operating frequency modes, depending on the load current level. At higher output Uses tiny multilayer inductors and capacitors loads, the buck regulators operate in PWM mode. When the Forced PWM and auto PWM/PSM modes load current falls below a predefined threshold, the regulators Out-of-phase operation for reduced input filtering operate in power save mode (PSM), improving the light-load 100% duty cycle low dropout mode efficiency. 24 A typical quiescent current per channel, no switching The two bucks operate out-of-phase to reduce the input LDO key specifications capacitor requirement and noise. Stable with 1 F ceramic output capacitors High PSRR The low quiescent current, low dropout voltage, and wide input 60 dB up to 10 KHz voltage range of the ADP5022 LDO extends the battery life of Low output noise portable devices. The LDO maintains power supply rejection 65 V rms output noise at VOUT3 = 3.3 V greater than 60 dB for frequencies as high as 10 kHz while Low dropout voltage: 150 mV 150 mA load operating with a low headroom voltage. 11 A typical ground current at no load Each regulator in the ADP5022 has a dedicated, independent APPLICATIONS enable pin. A high voltage level applied to the enable pin activates the respective regulator. The default output voltages are factory USB devices programmable and can be set to a wide range of options. Handheld products Multivoltage power for processors, ASICS, FPGAs, and RF chipsets ADP5022 L1 COUT 3 1H SW1 V OUT1 V = 2.4V VIN1 IN 600mA VOUT1 TO 5.5V BUCK1 C3 C4 ON C4 C2 EN1 10F 4.7F PGND1 OFF EN BK1 MODE PWM MODE C1 C2 PWM/PSM VIN2 L2 1H C3 MODE SW2 V OUT2 4.7F 600mA ON VOUT2 BUCK2 C5 5.0mm EN2 10F OFF PGND2 EN BK2 VDDA C1 VIN3 VOUT3 V LDO1 OUT3 1F ON 150mA EN3 C6 OFF EN LDO1 1F L1 COUT 1 COUT 2 AGND 4.7mm Figure 1. Typical Applications Circuit Figure 2. Typical PCB Layout Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20092010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08253-001 INDUCTOR INDUCTOR 08253-061ADP5022 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 Applications....................................................................................... 1 Power Management Unit........................................................... 16 General Description ......................................................................... 1 Buck Section................................................................................ 17 Revision History ............................................................................... 2 LDO Section ............................................................................... 18 Specifications..................................................................................... 3 Applications Information .............................................................. 19 Buck1 and Buck2 Specifications................................................. 4 Buck External Component Selection....................................... 19 LDO Specifications ...................................................................... 5 LDO Capacitor Selection .......................................................... 20 Absolute Maximum Ratings............................................................ 6 PCB Layout Guidelines.................................................................. 22 Thermal Data ................................................................................ 6 Evaluation Board schematics and Artwork ................................ 23 Thermal Resistance ...................................................................... 6 Suggested Layout........................................................................ 23 ESD Caution.................................................................................. 6 Outline Dimensions....................................................................... 25 Pin Configuration and Function Descriptions............................. 7 Ordering Guide .......................................................................... 25 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 10/10Rev. B to Rev. C Changes to Figure 2.......................................................................... 1 Changes to Table 9.......................................................................... 20 6/10Rev. A to Rev. B Changes to Ordering Guide .......................................................... 25 11/09Revision A: Initial Version Rev. C Page 2 of 28