Isolated, Half Bridge Gate Drivers with Adjustable Dead Time, 4 A Output Data Sheet ADuM4221/ADuM4221-1 FEATURES FUNCTIONAL BLOCK DIAGRAMS 4 A peak current (<2 RDSON x) ADuM4221 2.5 V to 6.5 V input supply voltage V V 1 16 DDA IA UVLO TSD 4.5 V to 35 V output supply voltage V V DECODE 15 2 OA IB UVLO VDD1 positive going threshold: 2.5 V maximum AND ENCODE LOGIC Multiple UVLO options for VDDA and VDDB positive going V GND 3 14 DD1 A threshold UVLO GND 1 4 13 NC Grade A: 4.5 V maximum CONTROL Grade B: 7.5 V maximum LOGIC DISABLE 12 NC 5 Grade C: 11.6 V maximum UVLO TSD V DT 6 11 DDB Precise timing characteristics 44 ns maximum propagation delay DECODE NC 10 V 7 OB ENCODE AND Adjustable dead time and dual input (ADuM4221) LOGIC V GND Adjustable dead time and single input (ADuM4221-1) DD1 8 9 B CMOS input logic levels NC = NO CONNECT High common-mode transient immunity: 150 kV/s Figure 1. ADuM4221 High junction temperature operation: 125C Default low output ADuM4221-1 V PWM 1 16 Safety and regulatory approvals (pending) UVLO TSD DDA UL recognition per UL 1577 NC V 2 DECODE 15 OA AND 5700 V rms for 1 minute duration ENCODE LOGIC CSA Component Acceptance Notice 5A V 3 14 GND DD1 A UVLO VDE certificate of conformity GND 4 13 NC 1 DIN V VDE V 0884-11: VIORM = 849 V peak CONTROL Increased creepage wide body, 16-lead SOIC IC LOGIC DISABLE 12 NC 5 APPLICATIONS UVLO TSD V DT 6 11 DDB Switching power supplies Isolated IGBT/MOSFET gate drives DECODE NC 10 V 7 OB ENCODE AND LOGIC Industrial inverters V GND DD1 9 8 B Gallium nitride (GaN)/silicon carbide (SiC) compatible GENERAL DESCRIPTION NC = NO CONNECT The ADuM4221/ADuM4221-1 are 4 A isolated, half bridge gate Figure 2. ADuM4221-1 drivers that employ the Analog Devices, Inc., iCoupler technology to provide independent and isolated high-side and low-side The ADuM4221/ADuM4221-1 each have built in overlap outputs. The ADuM4221/ADuM4221-1 provide 5700 V rms protection and allow dead time adjustment. A single resistor isolation in an increased creepage wide body, 16-lead SOIC IC. between the dead time pin (DT) and the GND1 pin sets the dead time on the secondary side between the high-side and the Combining high speed CMOS and monolithic transformer low-side outputs. technology, these isolation components provide outstanding performance characteristics superior to the alternatives, such An internal thermal shutdown (TSD) sets outputs low if the as the combination of pulse transformers and gate drivers. internal temperature on the ADuM4221/ADuM4221-1 exceeds The isolators operate with a logic input voltage ranging from the TSD temperature. As a result, the ADuM4221/ADuM4221-1 2.5 V to 6.5 V, providing compatibility with lower voltage systems. provide reliable control over the switching characteristics of In comparison to gate drivers employing high voltage level the insulated gate bipolar transistor (IGBT)/metal-oxide translation methodologies, the ADuM4221/ADuM4221-1 offer the semiconductor field effect transistor (MOSFET) configurations benefit of true, galvanic isolation between the input and each output. over a wide range of positive or negative switching voltages. 1 Protected by U.S. Patents 5,952,849 6,873,065 7,075,239. Other patents pending. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 2020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 17219-201 17219-001ADuM4221/ADuM4221-1 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics .......................................... 10 Applications ...................................................................................... 1 Theory of Operation ...................................................................... 14 General Description ......................................................................... 1 Applications Information ............................................................. 15 Functional Block Diagrams ............................................................. 1 PCB Layout ................................................................................. 15 Revision History ............................................................................... 2 Propagation Delay-Related Parameters .................................. 15 Specifications .................................................................................... 3 Peak Current Rating .................................................................. 15 Electrical Characteristics ............................................................. 3 Protection Features .................................................................... 15 Package Characteristics ............................................................... 4 Output Load Characteristics .................................................... 16 Regulatory Information ............................................................... 5 Adjustable Dead Time Control ................................................ 16 Insulation and Safety Related Specifications ............................ 5 Bootstrapped, Half Bridge Operation ..................................... 18 DIN V VDE V 0884-11 (VDE V 0884-11) Insulation Power Dissipation ...................................................................... 19 Characteristics .............................................................................. 6 DC Correctness and Magnetic Field Immunity .................... 19 Recommended Operating Conditions ...................................... 6 Insulation Lifetime ..................................................................... 20 Absolute Maximum Ratings ........................................................... 7 Outline Dimensions ....................................................................... 21 Thermal Resistance ...................................................................... 7 Ordering Guide .......................................................................... 21 ESD Caution.................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8 REVISION HISTORY 8/2020Rev. 0 to Rev. A Add ADuM4221-1 ............................................................. Universal Added Figure 2 Renumbered Sequentially .................................. 1 Changes to Input Supply Current, Quiescent Parameter, Table 1 ................................................................................................ 3 Changes to Table 7 ........................................................................... 7 Changes to Figure 4 Caption, Table 10 Caption, and Table 11 Caption ........................................................................................................ 8 Add Figure 5, Table 12, and Table 13 Renumbered Sequentially ... 9 Added Figure 10 ............................................................................. 10 Changes to Figure 8 Caption, Figure 9 Caption, and Figure 11 Caption ...................................................................................................... 10 Changes to Figure 12 Captions ............................................................. 11 Changes to Figure 28 and TSD Section ............................................... 15 Changes to Figure 30 and Adjustable Dead Time Control Section ....................................................................................................... 16 Added Figure 33 ....................................................................................... 17 Changes to Bootstrapped, Half Bridge Operation Section and Figure 34 Caption ........................................................................... 18 7/2020Revision 0: Initial Version Rev. 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