MAX19505 19-4314 Rev 1 9/10 Dual-Channel, 8-Bit, 65Msps ADC General Description Features The MAX19505 dual-channel, analog-to-digital convert- Very-Low-Power Operation (43mW/Channel at er (ADC) provides 8-bit resolution and a maximum sam- 65Msps) ple rate of 65Msps. 1.8V or 2.5V to 3.3V Analog Supply The MAX19505 analog input accepts a wide 0.4V to 1.4V input common-mode voltage range, allowing DC- Excellent Dynamic Performance coupled inputs for a wide range of RF, IF, and base- 49.8dBFS SNR at 70MHz band front-end components. The MAX19505 provides 69dBc SFDR at 70MHz excellent dynamic performance from baseband to high User-Programmable Adjustments and Feature input frequencies beyond 400MHz, making the device Selection through an SPI Interface ideal for zero-intermediate frequency (ZIF) and high- intermediate frequency (IF) sampling applications. The Selectable Data Bus (Dual CMOS or Single typical signal-to-noise ratio (SNR) performance is Multiplexed CMOS) 49.8dBFS and typical spurious-free dynamic range DCLK Output and Programmable Data Output (SFDR) is 69dBc at f = 70MHz and f = 65MHz. IN CLK Timing Simplifies High-Speed Digital Interface The MAX19505 operates from a 1.8V supply. Very Wide Input Common-Mode Voltage Range Additionally, an integrated, self-sensing voltage regula- tor allows operation from a 2.5V to 3.3V supply (AVDD). (0.4V to 1.4V) The digital output drivers operate on an independent Very High Analog Input Bandwidth (> 850MHz) supply voltage (OVDD) over the 1.8V to 3.5V range. Single-Ended or Differential Analog Inputs The analog power consumption is only 43mW per chan- nel at V = 1.8V. In addition to low operating AVDD Single-Ended or Differential Clock Input power, the MAX19505 consumes only 1mW in power- Divide-by-One (DIV1), Divide-by-Two (DIV2), and down mode and 15mW in standby mode. Divide-by-Four (DIV4) Clock Modes Various adjustments and feature selections are avail- able through programmable registers that are Twos Complement, Gray Code, and Offset Binary accessed through the 3-wire serial-port interface. Output Data Format Alternatively, the serial-port interface can be disabled, Out-of-Range Indicator (DOR) with the three pins available to select output mode, data format, and clock-divider mode. Data outputs are CMOS Output Internal Termination Options available through a dual parallel CMOS-compatible out- (Programmable) put data bus that can also be configured as a single Reversible Bit Order (Programmable) multiplexed parallel CMOS bus. Data Output Test Patterns The MAX19505 is available in a small 7mm x 7mm 48-pin thin QFN package and is specified over the Small, 7mm x 7mm 48-Pin Thin QFN Package with -40C to +85C extended temperature range. Exposed Pad Refer to the MAX19515, MAX19516, and MAX19517 data sheets for pin- and feature-compatible 10-bit, Ordering Information 65Msps, 100Msps, and 130Msps versions, respectively. PART TEMP RANGE PIN-PACKAGE Refer to the MAX19506 and MAX19507 data sheets for pin- and feature-compatible 8-bit, 100Msps and MAX19505ETM+ -40C to +85C 48 TQFN-EP* 130Msps versions, respectively. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Applications IF and Baseband Communications, Including Cellular Base Stations and Point-to-Point Microwave Receivers Ultrasound and Medical Imaging Portable Instrumentation and Low-Power Data Pin Configuration appears at end of data sheet. Acquisition Digital Set-Top Boxes SPI is a trademark of Motorola, Inc. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com. EVALUATION KIT AVAILABLEDual-Channel, 8-Bit, 65Msps ADC ABSOLUTE MAXIMUM RATINGS OVDD, AVDD to GND............................................-0.3V to +3.6V Continuous Power Dissipation (T = +70C) A CMA, CMB, REFIO, INA+, INA-, INB+, 48-Pin Thin QFN, 7mm x 7mm x 0.8mm INB- to GND ......................................................-0.3V to +2.1V (derate 40mW/C above +70C)................................3200mW CLK+, CLK-, SYNC, SPEN, CS, SCLK, SDIN Operating Temperature Range ...........................-40C to +85C to GND ..........-0.3V to the lower of (V + 0.3V) and +3.6V Junction Temperature......................................................+150C AVDD DCLKA, DCLKB, D7AD0A, D7BD0B, DORA, DORB Storage Temperature Range .............................-65C to +150C to GND..........-0.3V to the lower of (V + 0.3V) and +3.6V Lead Temperature (soldering, 10s) .................................+300C OVDD Soldering Temperature (reflow) .......................................+260C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V = V = 1.8V, internal reference, differential clock, V = 1.5V , f = 65MHz, A = -0.5dBFS, data output termination AVDD OVDD CLK P-P CLK IN = 50 , T = -40C to +85C, unless otherwise noted. Typical values are at T = +25C.) (Note 1) A A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 8 Bits Integral Nonlinearity INL f = 3MHz -0.3 0.0 +0.3 LSB IN Differential Nonlinearity DNL f = 3MHz -0.3 0.1 +0.3 LSB IN Offset Error OE Internal reference -0.4 0.1 +0.4 %FS Gain Error GE External reference = 1.25V -1.5 0.3 +1.5 %FS ANALOG INPUTS (INA+, INA-, INB+, INB-) (Figure 3) Differential Input-Voltage Range V Differential or single-ended inputs 1.5 V DIFF P-P Common-Mode Input-Voltage V (Note 2) 0.4 1.4 V CM Range Fixed resistance, common mode, and > 100 differential mode Input Resistance R k IN Differential input resistance, common mode 4 connected to inputs Switched capacitance common-mode input Input Current I 35 A IN current, each input C Fixed capacitance to ground, each input 0.7 PAR Input Capacitance pF C Switched capacitance, each input 1.2 SAMPLE CONVERSION RATE Maximum Clock Frequency f 65 MHz CLK Minimum Clock Frequency f 30 MHz CLK Data Latency Figures 9, 10 9 Cycles 2 MAX19505