APS25608N-OBR-BD AP Memory

APS25608N-OBRx DDR Octal SPI PSRAM Double-Data-Rate Octal SPI PSRAM Specifications Features Single Supply Voltage: Low Power Features: o VDD =1.62 to 1.98V o Partial Array Self-Refresh (PASR) o VDDQ =1.62 to 1.98V o Auto Temperature Compensated Self- Interface: Octal SPI with DDR mode, two bytes Refresh (ATCSR) self-managed by a built-in temperature sensor transfers per one clock cycle o Ultra Low Power Half Sleep mode with data Performance: Clock rate up to 200MHz, retention. (400MBps read/write throughput) Software reset Organization: 256Mb, 32M x 8bits with 2048 Reset pin available bytes per page o Column address: AY0 to AY10 Output driver LVCMOS with programmable o Row address: AX0 to AX13 drive strength Refresh: Self-managed Data mask (DM) for write operation Operating temperature range Data strobe (DQS) for high speed read operation o TC = -40C to +85C (standard range)* Write burst length, maximum 2048 Byte, o TC = -40C to +105C (extended range)* minimum 2 Byte. Typical mean Room Standby Current: Wrap & hybrid burst in 16/32/64/2K lengths. o 90A 25C (Standby mode) Linear Burst Command o 40A 25C (Half Sleep Mode with data Row Boundary Crossing (RBX) read operations retained) enabled via Mode Register Maximum Standby Current: o 1100A 105C o 680A 85C * please refer to Table 1 APM Octal PSRAM Datasheet.pdf - Rev. 1.0 Jul 27, 2020 1 of 29 AP Memory reserves the right to change products and/or specifications without notice 2020 AP Memory. All rights reserved APS25608N-OBRx DDR Octal SPI PSRAM Table of Contents 1 Table of Contents 1 Table of Contents ............................................................................................................. 2 2 Package Information ........................................................................................................ 4 2.1 Package Types : BGA 24b X8 (BD) ................................................................................... 4 2.2 Package Outline Drawing .................................................................................................... 5 2.2.1 BGA 24b , package code BD .................................................................................................. 5 3 Ordering Information ....................................................................................................... 6 4 Signal Table ...................................................................................................................... 7 5 Power-Up Initialization .................................................................................................... 8 5.1 Power-Up Initialization Method 1 (via. RESET pin) ........................................................... 8 5.2 Power-Up Initialization Method 2 (via. Global Reset) ........................................................ 9 6 Interface Description ..................................................................................................... 10 6.1 Address Space ................................................................................................................... 10 6.2 Burst Type & Length ......................................................................................................... 10 6.3 Command/Address Latching ............................................................................................. 10 6.4 Command Truth Table ...................................................................................................... 10 6.5 Read Operation ................................................................................................................. 11 6.6 Write Operation ................................................................................................................ 14 6.7 Control Registers ............................................................................................................... 15 6.8 Half Sleep Mode ................................................................................................................ 21 6.9 Deep Power Down Mode .................................................................................................. 22 7 Electrical Specifications: ................................................................................................ 23 7.1 Absolute Maximum Ratings .............................................................................................. 23 7.2 Pin Capacitance ................................................................................................................. 23 7.3 Decoupling Capacitor Requirement .................................................................................. 24 7.3.1 Low ESR cap C1: .................................................................................................................. 24 7.3.2 Large cap C2: ....................................................................................................................... 24 7.4 Operating Conditions ........................................................................................................ 24 7.5 DC Characteristics ............................................................................................................. 25 7.6 ISB Partial Array Refresh Current ...................................................................................... 26 7.7 AC Characteristics ............................................................................................................. 27 APM Octal PSRAM Datasheet.pdf - Rev. 1.0 Jul 27, 2020 2 of 29 AP Memory reserves the right to change products and/or specifications without notice 2020 AP Memory. All rights reserved