AT-32063 Low Current, High Performance NPN Silicon Bipolar Transistor Data Sheet Description Features High Performance Bipolar Transistor Optimized for The AT-32063 contains two high performance NPN bipolar LowC urrent,L ow VoltageOper ation transistors in a single SOT-363 package. The devices are 900 MHzP erformance:1.1 dB NF, 14.5 dB G unconnected, allowing flexibility in design. The pin-out A is convenient for cascode amplifier designs. The SOT-363 Characterizedf or End-of-Life BatteryU se (2.7 V) package is an industry standard plastic surface mount SOT-363 (SC-70) PlasticP ackage package. Tape-and-Reel Packaging Option Available The 3.2 micron emitter-to-emitter pitch and reduced Lead-free parasitic design of the transistor yields extremely high performance products that can perform a multiplicity of tasks. The 20 emitter finger interdigitated geometry yields a transistor that is easy to match to and extremely fast, with moderate power, low noise resistance, and low Surface Mount Package operating currents. SOT-363 (SC-70) Optimized performance at 2.7 V makes this device ideal for use in 900 MHz, 1.8 GHz, and 2.4 GHz battery operated systems as an LNA, gain stage, buffer, oscillator, or active mixer. Typical amplifier designs at 900 MHz yield 1.3 dB noise figures with 12 dB or more associated gain at a 2.7 V, 5 mA bias, with noise performance being relatively insensitive to input match. High gain capability at 1 V, 1 mA makes this device a good fit for 900 MHz pager ap- Pin Connections and Package Marking plications. Voltage breakdowns are high enough for use at5 volts. 1 6 B C 1 1 The AT-3 series bipolar transistors are fabricated using 2 5 an optimized version of Avagos 10 GHz f , 30 GHz f E E 1 2 t max 3 4 Self-Aligned-Transistor (SAT) process. The die are nitride C B 2 2 passivated for surface protection. Excellent device unifor- mity, performance and reliability are produced by the use of ion-implantation, self-alignment techniques, and gold metallization in thefabr icationof these devic es. 1 AT-32063 Absolute Maximum Ratings 2 Thermal Resistance : Absolute = 370C/W Symbol Parameter Units Maximum jc V Emitter-BaseVoltage V 1.5 EBO Notes: V Collector-BaseVoltage V 11 1. Permanent damagema yoc cur if any CBO of theselimits ar ee xceeded. V Collector-Emitter Voltage V 5.5 CEO 2. T = 25C. MountingSur face I CollectorCurrent mA 32 C 3. Derate at 2.7mW/C f or T > 94.5C. C 2,3 P PowerDissipation mW 150 T 4. 150mW per devic e. T JunctionTemperature C 150 j T Storage Temperature C -65 to150 STG Electrical Specifications, T = 25C A Symbol Parameters and Test Conditions Units Min. Typ. Max. 2 2 NF Noise Figure V = 2.7 V,I = 5 mA f =0.9 GHz dB 1.1 1.4 CE C 2 2 G Associated Gain V = 2.7 V, I = 5 mA f = 0.9 GHz dB 12.5 14.5 A CE C h ForwardC urrent Transfer Ratio V = 2.7 V, I = 5mA 50 270 FE CE C I Collector Cutoff Current V = 3 V A 0.2 CBO CB I Noise Figure V = 1 V A 1.5 EBO EB Notes: 1. Allda ta is perindividual tr ansistor. 2. Test circuit, Figure 1. Numbers reflect device performance de-embedded fromcir cuit losses. Input loss = 0.2 dB output loss =0.3 dB. 50 50 W=10 W=10 L=450 L=100 W=20 L=60 TESTCIRCUIT BOARDMATERIAL=0.047GETEK (e=4.3) DIMENSIONSINMILS NOTTOSCALE Figure 1. Test circuit for Noise Figure and Associated Gain. This circuit is a compromise match between best noise figure, best gain, stability, and a practical synthesizable match. 2