PI6C4853111 2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux Features Description F = 500MHz The PI6C4853111 is a high-performance low-skew 1-to-10 LVPECL MAX fanout buffer. The PI6C4853111 features two selectable differential 10 pairs of differential LVPECL outputs clock inputs and translates to ten LVPECL outputs. The CLK inputs Low additive jitter, <100fs 12k-20MHz accept LVPECL, LVDS, CML and SSTL signals. Selectable differential input pairs with single ended input PI6C4853111 is ideal for clock distribution applications such as option providing fanout for low noise SaRonix-eCera oscillators. Input CLK accepts: LVPECL, LVDS, CML, SSTL input level Output skew: 35ps (typ) o o Operating Temperature: -40 C to 85 C Core Power supply: 3.3V 10%, Output Power supply: 2.5V 5% & 3.3V 10% Packaging (Pb-free & Green): 32-pin TQFP (FA) Block Diagram Pin Configuration 24 23 22 21 20 19 18 17 V v DDO 25 16 DDO /Q2 Q7 15 26 Q2 14 /Q7 27 /Q1 Q8 28 13 Q1 12 /Q8 29 /Q0 Q9 30 11 Q0 10 /Q9 31 v v DDO 32 9 DDO 1 2 3 4 5 6 7 8 www.diodes.com March 2017 PI6C4853111 Rev B 1 17-0050 Diodes Incorporated V DD Q3 CLK SEL /Q3 CLK0 Q4 /CLK0 /Q4 NC Q5 CLK1 /Q5 /CLK1 Q6 V EE /Q6 PI6C4853111 (1) Pin Description Name Pin Type Description V 8 P Connect to negative power supply EE Clock select input. When high, selects CLK1 input. When low, selects CLK0 input. CLK SEL 2 I LVCMOS/LVTTL level with 50k pull down. CLK0 3 I Differential LVPECL clock input with 75k pull-down /CLK0 4 I Inverting differential LVPECL clock input. Defaults to V /2 if left floating. DD CLK1 6 I Differential LVPECL clock input with 75k pull-down /CLK1 7 I Inverting differential LVPECL clock input. Defaults to V /2 if left floating. DD NC 5 No Connect V 9,16, 25,32 P Output Power pin DDO V 1 P Core Power Supply DD Q3, Q3 24,23 O Differential output pair, LVPECL interface level. / Q2, Q2 27,26 O Differential output pair, LVPECL interface level. / Q1, Q1 29,28 O Differential output pair, LVPECL interface level. / Q0, Q0 31,30 O Differential output pair, LVPECL interface level. / Q9, Q9 11,10 O Differential output pair, LVPECL interface level. / Q8, Q8 13,12 O Differential output pair, LVPECL interface level. / Q7, Q7 15,14 O Differential output pair, LVPECL interface level. / Q6, Q6 18,17 O Differential output pair, LVPECL interface level. / Q5, Q5 20,19 O Differential output pair, LVPECL interface level. / Q4, Q4 22,21 O Differential output pair, LVPECL interface level. / Note: 1. I = Input, O = Output, P = Power supply connection. Pin Characteristics Symbol Parameter Conditions Min. Typ. Max. Units R Input Pullup/Pulldown Resistance 50 k Control Input Function Table Inputs Outputs 0 CLK0 1 CLK1 2 www.diodes.com March 2017 PI6C4853111 Rev B 17-0050 Diodes Incorporated