Product Information

CY7C344B-15WC

CY7C344B-15WC electronic component of E2v

Datasheet
CPLD MAX® Family 600 Gates 32 Macro Cells 0.65um Technology 5V 28-Pin Windowed CDIP

Manufacturer: E2v
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 172.5939 ea
Line Total: USD 172.59

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - WHS 1


Ships to you between Fri. 17 May to Thu. 23 May

MOQ : 1
Multiples : 1
1 : USD 172.5939
10 : USD 152.2827
50 : USD 143.8283
100 : USD 136.2568

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Operating Supply Voltage
Maximum Operating Temperature
Mounting Style
Brand
Frequency
Pin Count
Number Of Usable Gates
Propagation Delay Time
Macrocells
I/Os Max
Operating Temperature Classification
Operating Supply Voltage Min
Operating Temp Range
Rad Hardened
Operating Temperature Min
Memory Type
Package Type
In System Programmable
Number Of Logic Blocks/Elements
Family Name
Programmable
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1CY 7C34 4B fax id: 6101 CY7C344 CY7C344B 32-Macrocell MAX EPLD sents the densest EPLD of this size. Eight dedicated inputs Features and 16 bidirectional I/O pins communicate to one logic array High-performance, high-density replacement for TTL, block. In the CY7C344 LAB there are 32 macrocells and 64 74HC, and custom logic expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if 32 macrocells, 64 expander product terms in one LAB all of the I/O pins are driven by macrocell registers, there are 8 dedicated inputs, 16 I/O pins still 16 buried registers available. All inputs, macrocells, and 0.8-micron double-metal CMOS EPROM technology I/O pins are interconnected within the LAB. (CY7C344) The speed and density of the CY7C344/CY7C344B makes it Advanced 0.65-micron CMOS EPROM technology to a natural for all types of applications. With just this one device, increase performance (CY7C344B) the designer can implement complex state machines, regis- 28-pin 300-mil DIP, cerDIP or 28-pin HLCC, PLCC tered logic, and combinatorial glue logic, without using mul- package tiple chips. This architectural flexibility allows the Functional Description CY7C344/CY7C344B to replace multichip TTL solutions, whether they are synchronous, asynchronous, combinatorial, Available in a 28-pin 300-mil DIP or windowed J-leaded ce- or all three. ramic chip carrier (HLCC), the CY7C344/CY7C344B repre- [1] Logic Block Diagram Pin Configurations HLCC 15(22) INPUT INPUT 1(8) Top View 15(23) INPUT INPUT/CLK 2(9) 27(6) INPUT INPUT 13(20) 28(7) INPUT INPUT 14(21) 432 1 28 27 26 5 25 I/O I/O 6 24 I/O INPUT MACROCELL 2 MACROCELL 1 I/O 3(10) 7 INPUT 23 INPUT I/O 4(11) MACROCELL 4 MACROCELL 3 8 INPUT 22 INPUT G 9 I/O 5(12) INPUT/CLK INPUT MACROCELL 6 MACROCELL 5 I 21 L 10 I/O 20 INPUT I/O 6(13) MACROCELL 8 MACROCELL 7 O O 11 I/O I/O 19 I/O 9(16) 12 13 14 1516 1718 MACROCELL 10 MACROCELL 9 B C I/O 10(17) MACROCELL 12 MACROCELL 11 A O C3442 I/O 11(18) MACROCELL 14 MACROCELL 13 L N I/O 12(19) MACROCELL 16 MACROCELL 15 CerDIP T I/O 17(24) MACROCELL 18 MACROCELL 17 Top View B R I/O 18(25) MACROCELL 20 MACROCELL 19 U INPUT INPUT 1 28 O I/O 19(26) MACROCELL 22 MACROCELL 21 S INPUT/CLK 2 27 INPUT L I/O 20(27) I/O I/O MACROCELL 24 MACROCELL 23 3 26 I/O I/O I/O 23(2) 4 25 MACROCELL 26 MACROCELL 25 I/O I/O 5 24 I/O 24(3) MACROCELL 28 MACROCELL 27 I/O I/O 6 23 I/O 25(4) MACROCELL 30 MACROCELL 29 V V CC 7 22 CC I/O 26(5) MACROCELL 32 MACROCELL 31 GND 8 21 GND I/O I/O 9 20 I/O I/O 10 19 I/O I/O C3441 11 18 32 64 EXPANDER PRODUCT TERM ARRAY I/O I/O 12 17 INPUT INPUT 13 16 INPUT INPUT 14 15 C3443 Selection Guide 7C34415 7C34420 7C34425 7C344B10 7C344B12 7C344B15 7C344B20 7C344B25 Maximum Access Time (ns) 10 12 15 20 25 Maximum Commercial 200 200 200 200 200 Operating Military 220 220 220 Current (mA) Industrial 220 220 220 220 Maximum Standby Commercial 150 150 150 150 150 Current (mA) Military 170 170 170 Industrial 170 170 170 170 Shaded area contains preliminary information. Note: 1. Numbers in () refer to J-leaded packages. Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600 January 1990 Revised October 1995 CY7C344 CY7C344B DC Output Current, per Pin ......................25 mA to +25 mA Maximum Ratings [2] DC Input Voltage .........................................3.0V to +7.0V (Above which the useful life may be impaired. For user guide- DC Program Voltage .................................................. +13.0V lines, not tested.) Storage Temperature ................................. 65C to +150C Operating Range Ambient Temperature with Ambient Power Applied...................................................0C to +70C Range Temperature V CC Maximum Junction Temperature (Under Bias)............. 150C Commercial 0C to +70C 5V 5% Supply Voltage to Ground Potential............... 2.0V to +7.0V Industrial 40C to +85C 5V 10% Maximum Power Dissipation...................................1500 mW Military 55C to +125C (Case) 5V 10% DC V or GND Current............................................500 mA CC Static Discharge Voltage (per MIL-STD-883, Method 3015)..............................>2001V [3] Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit V Output HIGH Voltage V = Min., I = 4.0 mA 2.4 V OH CC OH V Output LOW Voltage V = Min., I = 8 mA 0.45 V OL CC OL V Input HIGH Level 2.2 V +0.3 V IH CC V Input LOW Level 0.3 0.8 V IL I Input Current GND V V 10 +10 A IX IN CC I Output Leakage Current V = V or GND 40 +40 A OZ O CC [4, 5] I Output Short Circuit Current V = Max., V = 0.5V 30 90 mA OS CC OUT I Power Supply V = V or GND (No Load) Commercial 150 mA CC1 I CC Current (Standby) Military/Industrial 170 mA I Power Supply Current V = V or GND (No Load) Commercial 200 mA CC2 I CC [4,6] f = 1.0 MHz Military/Industrial 220 mA t Recommended Input Rise Time 100 ns R t Recommended Input Fall Time 100 ns F Capacitance Parameter Description Test Conditions Max. Unit C Input Capacitance V = 2V, f = 1.0 MHz 10 pF IN IN C Output Capacitance V = 2.0V, f = 1.0 MHz 10 pF OUT OUT [7] AC Test Loads and Waveforms R1 464 R1 464 5V 5V ALL INPUT PULSES OUTPUT OUTPUT 3.0V 90% 90% 10% R2 R2 10% 50 pF 5pF GND t f 250 250 6ns 6ns INCLUDING t t R F JIGAND SCOPE C3444 C3445 (a) (b) Equivalent to: THVENIN EQUIVALENT (commercial/military) 163 OUTPUT 1.75V C3446 Notes: 2. Minimum DC input is 0.3V. During transitions, the inputs may undershoot to 2.0V for periods less than 20 ns. 3. Typical values are for T = 25C and V = 5V. A CC 4. Guaranteed by design but not 100% tested. 5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V = 0.5V has been chosen to avoid OUT test problems caused by tester ground degradation. 6. Measured with device programmed as a 16-bit counter. 7. Part (a) in AC Test Load and Waveforms is used for all parameters except t and t , which is used for part (b) in AC Test Load and Waveforms. All external timing ER XZ parameters are measured referenced to external pins of the device. 2

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8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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