FUJITSU MICROELECTRONICS PG00-00091-3E PRODUCT GUIDE 2009.10 Product Guide ASSPMemoryASIC Technical Documentation of Electronic Devices DATA BOOK PRODUCT GUIDE DATA SHEET MANUAL (GENERAL) (DVD) FUJITSU SEMICONDUCTOR DS04-27211-5E DATA SHEET ASSP For Power Supply Applications Semiconductor Data Book FUJITSU SEMICONDUCTOR BIPOLAR DATA SHEET DS04-27211-5E Switching Regulator Controller ASSP (Supporting External Synchronization) ASSP For Power Supply Applications CD-ROM FUJITSU SEMICONDUCTOR DATA SHEET BIPOLAR DS04-27211-5E MB3789 ACCD-10131D-10131 Switching Regulator Controller MMADE IN ADE IN JAPANAN (Supporting External Synchronization) foorr WindWindowwss / Macinto/ Macintosshh CD00-00031-3E ASSP For Power Supply Applications DESCRIPTION BIPOLAR The MB3789 is a PWM (pulse width modulation) switching regulator controller supporting an external sync signal. The MB3789 incorporates two error amplifiers which can be used respectively for voltage control and current MB3789 control, allowing the IC to serve as a DC/DC converter with current regulating functions. Switching Regulator ContrThe MBoller3789 is the ideal IC for supplying power to the back-lighting fluorescent tube for a liquid crystal display (LCD) device such as a camera-integrated VTR. Technical Communication Department, Electronic Devices (Supporting External Synchronization) DESCRIPTION FEATURES The MB3789 is a PWM (pulse width modulation) s Wide range of operwitching ating powregulator econtroller r supply vsupporoltages: ting an e3 V to 18 xterVnal sync signal. MB3789 The MB3789 incorporates two error amplifiers which can be used respectiv Low current consumption: 1.5 mA (Typ)ely for voltage control and current control, allowing the IC to serve as a DC/DC con Wide input vveroltage range of error amplifierter with current regulating functions: 0.2 V to . VCC 1.8 V The MB3789 is the ideal IC for supplying po Built-in twwer o error amplifierto the back-lighting fluorescent tube for a liquid crystal display (LCD) device such as a camera-integrated VTR. Oscillator capable of operating with an external sync signal DESCRIPTION FEATURES Built-in timer latch short protection circuit Variable dead time provides control over total operating range The MB3789 is a PWM (pulse width modulation) s Wide range of operating power supply witching regulator controller Output supporting a power MOSFETsupporvoltages: ting 3an e V to 18 xternal sync signalV . The MB3789 incorporates two error amplifiers which can be used respectiv Low current consumption: 1.5 mA (T 16-pin SSOP package mountable at high densityyp)ely for voltage control and current control, allowing the IC to serve as a DC/DC con Wide input vervoter with current regulating functionsltage range of error amplifier: 0.2 V to . VCC 1.8 V The MB3789 is the ideal IC for supplying po Built-in twwer o error amplifierto the back-lighting fluorescent tube fPACKAGE or a liquid crystal display (LCD) device such as a camera-integrated VTR. Oscillator capable of operating with an external sync signal Built-in timer latch short protection circuit 16-pin Plastic SSOP FEATURES Variable dead time provides control over total operating range Wide range of operating power supply Output supporting a power MOSFETvoltages: 3 V to 18 V Low current consumption: 1.5 mA (Typ) Wide input voltage range of error amplifier 16-pin SSOP package mountable at high density: 0.2 V to VCC 1.8 V Built-in two error amplifier PACKAGE Oscillator capable of operating with an external sync signal Built-in timer latch short protection circuit 16-pin Plastic SSOP Variable dead time provides control over total operating range Output supporting a power MOSFET (FPT-16P-M05) 16-pin SSOP package mountable at high density PACKAGE 16-pin Plastic SSOP (FPT-16P-M05) (FPT-16P-M05) ASSPMemoryASIC FUJITSU SEMICONDUCTOR DATA SHEET DS05-11440-2E MEMORY FUJITSU SEMICONDUCTOR CMOS DS05-11440-2E DATA SHEET 128 M-BIT (4-BANK 1 M-WORD 32-BIT) SINGLE DATA RATE I/F FCRAMTM Memory MEMORY Consumer/Embedded Application Specific Memory for SiP FUJITSU SEMICONDUCTOR CMOS DATA SHEET DS05-11440-2E 128 M-BIT (4-BANK MB81E 1 M-WS123245-10ORD 32-BIT) TM SINGLE DATA RATE I/F FCRAM DESCRIPTION MEMORY Consumer/Embedded Application The Fujitsu MB81ES123245 is a Single Data Rate InSpecific Memory fterface Faost Cycle Random Access Memorr SiP y (FCRAM*) containing 134,217,728 memory cells accessible in a 32-bit format. The MB81ES123245 features a fully synchro- CMOS nous operation referenced to a positive clock edge whereby all operations are synchronized at a clock input which 128 M-BIT (4-BANK MB81E 1 M-WS123245-10ORD enables high perf 32-BIT) ormance and simple user interface coexistence. SINGLE DATA RATE I/F FCRAMTMThe MB81ES123245 is utilized using a Fujitsu advanced FCRAM core technology and designed for low power DESCRIPTION consumption and low voltage operation than regular synchronous DRAM (SDRAM) . Consumer/Embedded Application Specific Memory fThe MB81ES123245 is dedicated for SiPor SiP (System in a Package) , and ideally suited for various embedded/ The Fujitsu MB81ES123245 is a Single Data Rate Inconsumer applications terface Fincluding ast Cycle Random Access Memordigital AVs and image processing y (FCRAM*)where a large band width and low power containing 134,217,728 memory cells consumption memoraccessible in a 32-bit fy is needed. ormat. The MB81ES123245 features a fully synchro- nous operation referenced to a positive clock edge whereby all operations are synchronized at a clock input which MB81ES123245-10enables high performance and simple user interf* : FCRAM is a trademarace coek of Fujitsu Limited, Jxistence. apan. The MB81ES123245 is utilized using a Fujitsu advanced FCRAM core technology and designed for low power consumption and low voltage operation than regular synchronous DRAM (SDRAM) . DESCRIPTION The Fujitsu MB81ES123245 is a Single Data Rate InThe MB81ES123245 is dedicated fterface Fast Cycle Random Access MemorPRor SiP (System in a ODUCT LINEUPPackage) , y (FCRAM*)and ideally suited for various embedded/ containing 134,217,728 memory cells consumer applications including digital Aaccessible in a 32-bit format. The MB81ES12Vs and 3245 fimage processing where a large band width and loeatures a fully synchro- w power nous operation referenced to a positivconsumption memore clock edge wherebyy all operations is needed. are synchronized at a clocParamk input whicheter MB81ES123245-10 enables high performance and simple user interf* : FCRAM is a trademarace coexistencek of Fujitsu Limited, J. apan. CL = 2 54 MHz Clock Frequency (Max) The MB81ES123245 is utilized using a Fujitsu advanced FCRAM core technology and designed for low power CL = 3 108 MHz consumption and low voltage operation than regular synchronous DRAM (SDRAM) . CL = 2 18.5 ns The MB81ES123245 is dedicated for SiP (System in a Package) , and ideally Burst Mode Cycle Time (Min) suited for various embedded/ consumer applications including digital APRODUCT LINEUPVs and image processing where a large band width and low power CL = 3 9.2 ns consumption memory is needed. Parameter MB8CL1E=S 2123245-10 9 ns Access Time from CLK (Max) * : FCRAM is a trademark of Fujitsu Limited, JClock Frequency (Max) apan. CL = 2 CL5=4 3MHz 7 ns Operating CCLurre=n t3 (Max) (64 page length) 108 MHz 35 mA Power Down Mode Current (Max) (IDD2PS) 0.5 mA Burst Mode Cycle Time (Min) CL = 2 18.5 ns PRODUCT LINEUP Self-Refresh Current (Max) CL = 3 Tj =+359.C2 nMsax 200 A Parameter Access Time from CLK (Max) MB81CLES=1 223245-10 9 ns CL = 2 CL54 =M 3Hz 7 ns Clock Frequency (Max) Operating Current (Max) (64 page length) 35 mA CL = 3 108 MHz Power Down Mode Current (Max) (ICL = 2 DD2PS) 18.5 ns 0.5 mA Burst Mode Cycle Time (Min) Self-Refresh Current (Max) Tj =+35 C Max 200 A CL = 3 Copyright2006 FUJITSU LIMITED All rights reserved9.2 ns CL = 2 9 ns Access Time from CLK (Max) CL = 3 7 ns Operating Current (Max) (64 page length) 35 mA Power Down Mode Current (Max) (IDD2PS) 0.5 mA Self-Refresh Current (Max) Copyright2006 FUJITSU LIMITED All rights reservedTj =+35 C Max 200 A Copyright2006 FUJITSU LIMITED All rights reserved FUJITSU SEMICONDUCTOR DATA SHEET DS06-20210-2E Semicustom FUJITSU SEMICONDUCTOR DATA SHEET CMOS DS06-20210-2E Standard Cell ASIC Semicustom FUJITSU SEMICONDUCTOR CMOS DATA SHEET DS06-20210-2E CS101 Series Standard Cell DESCRIPTION Semicustom CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies users demands for lower power consumption and higher speed. The leakage current of the transistors is the minimum level in the industry. Three CMOS types of core transistors with a different threshold voltage can be mixed according to user application. CS101 SerieThe design rs ules match industry standards, and a wide range of IP macros are available for use. As well as providing a maximum of 100 million gates, approximately twice the level of integration achieved in Standard Cell DESCRIPTION previous products, the power consumption per gate is also reduced by about half to 2.7 nW. Also, using the high- CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies userspeed library increases the speed by a factor of apprs demands foximately 1.or lo3w, with a gaer power te delay time of 12 ps. consumption and higher speed. The leakage current of the transistors is the minimum level in the industry. Three types of core transistors with a different threshold voltage can be mixed according to user application. CS101 Series FEATURES The design rules match industry standards Technolog, and a wide ry ange of IP macros are a : 90 nm Si gate CMOSvailable for use. As well as providing a maximum of 100 million gates, approximately twice 7- to 10-metal lathe level of inteyers. gration achieved in DESCRIPTION previous products, the power consumption per gate is also reduced by about half to 2.7 nW. Also, using the high- speed library increases the speed by a factor of approximately 1.3, with a gaLow-K (lote delaw pery time of 12 psmittivity) mater. ial is used for all dielectric inter-layers. CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies users demands for lower powThree differ erent types of core transistors (low leak, standard, and high speed) consumption and higher speed. The leakage current of the transistors is the minimum level in the industry. Threcan be used on the same chipe . types of core transistors with a different threshold FEATUREvSoltage can be mixed according to user application. The design rules comply with industry standard processes. The design rules match industry standards, and a wide range of IP macros are a Power supply vvailable foor usltagee. : +1.2 V 0.1 V (standard) Technology : 90 nm Si gate CMOSOperation junction temperature : 40 C to + 125 C (standard) As well as providing a maximum of 100 million gates, approximately twice the le7- to 10-metal laGate delavel yof integ timeyersration achie. ved in : tpd = 12 ps (1.2 V, Inverter, F/O = 1) previous products, the power consumption per gate is also reduced by about half to 2.7 nWLoGw-K (loate powwe perr consumptiom. Alsoittivity) mater, using the high-n ial is used f : Pd = 2.7 nW/MHz/BC (1.2 Vor all dielectric inter-la,y 2 NANDers. , F/O = 1) speed library increases the speed by a factor of approximately 1.3, with a gaThree diffHte delaigh levy time of 12 pseerent types of core trl of integration. ansistors : Up to 91 million gates (low leak, standard, and high speed) can be used on the same chip. The design rReduced chip siules comply with industrzed realized by I/O with pad.y standard processes. FEATURES Power supply voltage : +S1.2 V uppor 0.1 V (standard) t for a wide range of cell sets (from low power versions to ultra high speed versions). Technology : 90 nm Si gate CMOS Operation junction temperature : C 40 ompliance with industC to + 125 C (standard)ry standard design rules enables non-Fujitsu commercial macros to be easily incorpo- 7- to 10-metal la Gate delay timeyers. : tpd rate= 12 ps (1.2 Vd. , Inverter, F/O = 1) Low-K (low permittivity) material is used f Compiled cell (RAM, or all dielectric inter-laROyM, others)ers. Gate power consumption : Pd Suppor= 2.7 nW/MHz/BC (1.2 Vt for ultra high speed (up to 10 Gbps) interf, 2 NAND, F/O = 1) ace macros. Three diff High leerent types of core trvel of integration ansistors : Up to 91 million gates (loSpecial interfw leak, standard, and high speed) aces (LVDS, SSTL2, etc.) can be used on the same chip Reduced chip sized realized b. y I/O with pad. Supports use of industry standard libraries (.LIB). The design r Support fuoles comply with industrr a wide range of cell sets (from loy standard processes Uses industw pory standard tools and suppower v.ersions to ultra high speed vrts the optimum tools fersions). or the application. Power supply voltage : +1.2 V Compliance with indust 0.1 V (standard) ry standard design rules enables non-Fujitsu commercial macros to be easily incorpo- Operation junction temperature : 40 raC to ted. + 125 C (standard) (Continued) Gate delay time : tpd =C 12 ps (1.2 Vompiled cell (RAM, , InverterR, F/O OM, others)= 1) Gate power consumption : Pd =S 2.7 nW/MHz/BC (1.2 Vupport for ultra high speed (up to 10 Gbps) interf, 2 NAND, F/O = 1) ace macros. High level of integration : Up to 91 million gates Special interfaces (LVDS, SSTL2, etc.) Reduced chip sized realized by I/O with pad Suppor. ts use of industry standard libraries (.LIB). Support for a wide range of cell sets (from lo Uses industw powry standard tools and suppoer versions to ultra high speed vrts the optimum tools ersions). for the application. Compliance with industry standard design rules enables non-Fujitsu commercial macros to be easily incorpo- (Continued) rated. Compiled cell (RAM, ROM, others) Support for ultra high speed (up to 10 Gbps) interface macros. Special interfaces (LVDS, SSTL2, etc.) Supports use of industry standard libraries (.LIB). Uses industry standard tools and supports the optimum tools for the application. (Continued) FUJITSU SEMICONDUCTOR DS07-12614-2E DATA SHEET 8-bit Proprietary Microcontrollers FUJITSU SEMICONDUCTOR DATA SHEET CMOS DS07-12614-2E Microcontroller 2 F MC-8FX MB95100AM Series 8-bit Proprietary Microcontrollers FUJITSU SEMICONDUCTOR DATA SHEET CMOS MB95108AM/F104AMDS07-12614-2ES/F104ANS/F104AJS/F106AMS/F106ANS/F106AJS/ MB95F108AMS/F108ANS/F108AJS/F104AMW/F104ANW/F104AJW/F106AMW/ MB95F106ANW/F106AJW/F108AMW/F108ANW/F108AJW/FV100D-103 2 F MC-8FX MB95100AM DESCRIPTION Series 8-bit Proprietary Microcontrollers The MB95100AM series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, MB95108AM/F104AMS/F104ANthe microcontrollers contain a vS/F104AJS/F106AMariety of perS/F106ANipheral functionS/F106AJs. S/ CMOS MB95F108AMS/F108ANSNote : F/F108AJ2MC is the abbrS/F104AMW/F104ANW/F104AJW/F106AMW/eviation of FUJITSU Flexible Microcontroller. MB95F106ANW/F106AJW/F108AMW/F108ANW/F108AJW/FV100D-103 F2MC-8FX MB95100AM Series DESCRIPTION FEATURE The MB95100AM series is general-pur F2MC-8FX CPU corepose, single-chip microcontrollers. In addition to a compact instruction set, MB95108AM/F104AMS/F104ANthe microcontrollers contain a vS/F104AJS/F106AMariety of perSInstruction set optimized for controllers/F106ANipheral functionS/F106AJs. S/ MB95F108AMS/F108ANS/F108AJ2 S/F104AMW/F104ANW/F104AJW/F106AMW/ Multiplication and division instructions Note : F MC is the abbreviation of FUJITSU Fl 16-bit arexibithmetic operationsle Microcontroller. MB95F106ANW/F106AJW/F108AMW/F108ANW/F108AJW/FV100D-103 Bit test branch instruction Bit manipulation instructions etc. DESCRIPTION FEATURE Clock F2MC-8FX CPU core Main clock The MB95100AM series is general-purInstruction set optimized for controllerspose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of per Multiplication and division instipheral functions. ructions Main PLL clock Note : F2MC is the abbreviation of FUJITSU Fl 16-bit arexible Microcontrollerithmetic operations. Sub clock (for dual clock product) Sub PLL clock (for dual clock product) Bit test branch instruction (Continued) FEATURE Bit manipulation instructions etc. 2 Clock F MC-8FX CPU core Main clock Instruction set optimized for controllers Main PLL clock Multiplication and division instructions Sub clock (for dual clock product) 16-bit arithmetic operations Sub PLL clock (for dual clock product) Bit test branch instruction (Continued) Bit manipulation instructions etc. Be sure to refer to the Check Sheet for the latest cautions on development. Clock Main clock Check Sheet is seen at the following support page Main PLL clock URL :