THIS SPEC IS OBSOLETE Spec No: 001-06551 Spec Title: CY7C1566V18/CY7C1577V18/ CY7C1568V18/ CY7C1570V18, 72-MBIT DDR-II+ SRAM 2-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) Sunset Owner: Jayasree Nayar (njy) Replaced by: NONE CY7C1566V18, CY7C1577V18 CY7C1568V18, CY7C1570V18 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) Data valid pin (QVLD) to indicate valid data on the output 400 MHz clock for high bandwidth Synchronous internally self-timed writes 1 2-word burst for reducing address bus frequency Core V = 1.8V 0.1V IO V = 1.4V to V DD DDQ DD Double Data Rate (DDR) interfaces HSTL inputs and variable drive HSTL output buffers (data transferred at 800 MHz) at 400 MHz Available in 165-Ball FBGA package (15 x 17 x 1.4 mm) Available in 2.5 clock cycle latency Offered in both Pb-free and non Pb-free packages Two input clocks (K and K) for precise DDR timing JTAG 1149.1 compatible test access port SRAM uses rising edges only Delay Lock Loop (DLL) for accurate data placement Echo clocks (CQ and CQ) simplify data capture in high-speed systems Configurations With Read Cycle Latency of 2.5 cycles: CY7C1566V18 8M x 8 CY7C1577V18 8M x 9 CY7C1568V18 4M x 18 CY7C1570V18 2M x 36 Functional Description The CY7C1566V18, CY7C1577V18, CY7C1568V18, and capturing data from each individual DDR SRAM in the system CY7C1570V18 are 1.8V Synchronous Pipelined SRAMs design. equipped with DDR-II+ architecture. The DDR-II+ consists of an All synchronous inputs pass through input registers controlled by SRAM core with advanced synchronous peripheral circuitry. the K or K input clocks. All data outputs pass through output Addresses for read and write are latched on alternate rising registers controlled by the K or K input clocks. Writes are edges of the input (K) clock. Write data is registered on the rising conducted with on-chip synchronous self-timed write circuitry. edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words (CY7C1566V18), 9-bit words (CY7C1577V18), 18-bit words (CY7C1568V18), or 36-bit words (CY7C1570V18) that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs, D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-06551 Rev. *G Revised November 15, 2010 + Feedback