CY14C512I CY14B512I CY14E512I 2 512-Kbit (64 K 8) Serial (I C) nvSRAM with Real Time Clock 1512-Kbit (64 K 8) Serial (I2C) nvSRAM with Real Time Clock 2 I C access to special functions Features Nonvolatile STORE/RECALL 512-Kbit nonvolatile static random access memory (nvSRAM) 8-byte serial number Internally organized as 64 K 8 Manufacturer ID and Product ID STORE to QuantumTrap nonvolatile elements initiated Sleep mode 2 automatically on power-down (AutoStore) or by using I C Low power consumption command (Software STORE) or HSB pin (Hardware STORE) Average active current of 1 mA at 3.4 MHz operation RECALL to SRAM initiated on power-up (Power-Up Average standby mode current of 250 A 2 RECALL) or by I C command (Software RECALL) Sleep mode current of 8 A Automatic STORE on power-down with a small capacitor Industry standard configurations High reliability Operating voltages: Infinite read, write, and RECALL cycles CY14C512I: V = 2.4 V to 2.6 V CC 1 million STORE cycles to QuantumTrap CY14B512I: V = 2.7 V to 3.6 V CC Data retention: 20 years at 85 C CY14E512I: V = 4.5 V to 5.5 V CC Real Time Clock (RTC) Industrial temperature Full-featured RTC 16-pin small outline integrated circuit (SOIC) package Watchdog timer Restriction of hazardous substances (RoHS) compliant Clock alarm with programmable interrupts Backup power fail indication Overview Square wave output with programmable frequency (1 Hz, 512 Hz, 4096 Hz, 32.768 kHz) The Cypress CY14C512I/CY14B512I/CY14E512I combines a 2 Capacitor or battery backup for RTC 512-Kbit nvSRAM with a full-featured RTC in a monolithic 2 Backup current of 0.45 A (typical) integrated circuit with serial I C interface. The memory is 2 1 organized as 64K words of 8 bits each. The embedded High-speed I C interface nonvolatile elements incorporate the QuantumTrap technology, Industry standard 100 kHz and 400 kHz speed creating the worlds most reliable nonvolatile memory. The Fast mode Plus 1 MHz speed SRAM provides infinite read and write cycles, while the High speed 3.4 MHz QuantumTrap cells provide highly reliable nonvolatile storage of Zero cycle delay reads and writes data. Data transfers from SRAM to the nonvolatile elements Write protection (STORE operation) takes place automatically at power-down.On power-up, data is restored to the SRAM from the nonvolatile Hardware protection using Write Protect (WP) pin memory (RECALL operation). The STORE and RECALL Software block protection for one-quarter, one-half, or entire 2 operations can also be initiated by the user through I C array commands. For a complete list of related documentation, click here. Serial Number Logic Block Diagram 8 x 8 V V V V CC CAP RTCcap RTCbat Manufacturer ID / Product ID Power Control Memory Control Register Block Command Register Quantum Trap 64 K x 8 Sleep STORE SRAM Control Registers Slave SDA 2 64 K x 8 I C Control Logic Memory RECALL SCL Memory Slave Slave Address Address and Data A2, A1, A0 RTC Slave Control Decoder WP X in RTC Control Logic INT/SQW Registers Counters X out Notes 2 1. The I C nvSRAM is a single solution which is usable for all four speed modes of operation. As a result, some I/O parameters are slightly different than those on chips which support only one mode of operation. Refer to AN87209 for more details. 2 2. Serial (I C) nvSRAM will be referred to as nvSRAM throughout the datasheet. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-64879 Rev. *I Revised November 5, 2014CY14C512I CY14B512I CY14E512I Contents Pinout ................................................................................3 Programmable Square Wave Generator ...................22 Pin Definitions ..................................................................3 Power Monitor ........................................................... 22 I2C Interface ......................................................................4 Backup Power Monitor .............................................. 22 Protocol Overview ............................................................4 Interrupts ...................................................................22 I2C Protocol Data Transfer .......................................4 Interrupt Register ....................................................... 22 Data Validity ................................................................5 Flags Register ........................................................... 23 START Condition (S) ...................................................5 RTC External Components ....................................... 24 STOP Condition (P) .....................................................5 PCB Design Considerations for RTC ............................ 25 Repeated START (Sr) .................................................5 Layout requirements .................................................. 25 Byte Format .................................................................5 Maximum Ratings ........................................................... 30 Acknowledge / No-acknowledge .................................5 Operating Range ............................................................. 30 High-Speed Mode (Hs-mode) .....................................6 DC Electrical Characteristics ........................................ 30 Slave Device Address .................................................7 Data Retention and Endurance ..................................... 31 Write Protection (WP) ..................................................9 Thermal Resistance ........................................................ 31 AutoStore Operation ....................................................9 AC Test Loads and Waveforms ..................................... 32 Hardware STORE and HSB pin Operation .................9 AC Test Conditions ........................................................ 32 Hardware RECALL (Power Up) ...................................9 RTC Characteristics ....................................................... 32 Write Operation .........................................................10 AC Switching Characteristics ....................................... 33 Read Operation .........................................................10 Switching Waveforms .................................................... 33 Memory Slave Access ...............................................10 nvSRAM Specifications ................................................. 34 RTC Registers Slave Access ....................................14 Switching Waveforms .................................................... 34 Control Registers Slave .............................................16 Software Controlled STORE/RECALL Cycles .............. 35 Serial Number .................................................................18 Switching Waveforms .................................................... 35 Serial Number Write ..................................................18 Hardware STORE Cycle ................................................. 36 Serial Number Lock ...................................................18 Switching Waveforms .................................................... 36 Serial Number Read ..................................................18 Ordering Information ...................................................... 37 Device ID .........................................................................19 Ordering Code Definitions ......................................... 37 Executing Commands Using Command Register .....19 Package Diagram ............................................................ 38 Real Time Clock Operation ............................................20 Acronyms ........................................................................39 nvTIME Operation .....................................................20 Document Conventions ................................................. 39 Clock Operations .......................................................20 Units of Measure ....................................................... 39 Reading the Clock .....................................................20 Document History Page ................................................. 40 Setting the Clock .......................................................20 Sales, Solutions, and Legal Information ...................... 42 Backup Power ...........................................................20 Worldwide Sales and Design Support ....................... 42 Stopping and Starting the Oscillator ..........................20 Products ....................................................................42 Calibrating the Clock .................................................21 PSoC Solutions ...................................................... 42 Alarm .........................................................................21 Cypress Developer Community ................................. 42 Watchdog Timer ........................................................21 Technical Support ..................................................... 42 Document Number: 001-64879 Rev. *I Page 2 of 42