CY2291 Three-PLL General Purpose EPROM Programmable Clock Generator Three-PLL General Purpose EPROM Programmable Clock Generator Features Functional Description Three integrated phase-locked loops The CY2291 is a third-generation family of clock generators. The CY2291 is upwardly compatible with the industry standard EPROM programmability ICD2023 and ICD2028 and continues their tradition by providing a high level of customizable features to meet the diverse clock Factory-programmable (CY2291) or field-programmable synchronous systems. (CY2291F) device options All parts provide a highly configurable set of close for PC Low-skew, low-jitter, high-accuracy outputs motherboard applications. Each of four configurable clock Power-management options (Shutdown, OE, Suspend) outputs (CLKA-CLKD) can be assigned 1 of 30 frequencies in any combination. Multiple outputs configured for the same or Frequency select option related 3 frequencies have low (<500 ps) skew, in effect providing on-chip buffering for heavily loaded signals. Smooth slewing on CPUCLK The CY2291 can be configured for either 5 V or 3.3 V operation. Configurable 3.3 V or 5 V operation The internal ROM tables use EPROM technology, allowing full 20-pin SOIC Package customization of output frequencies. The reference oscillator has been designed for 10 MHz to 25 MHz crystals, providing additional flexibility. No external components are required with this crystal. Alternatively, an external reference clock of frequency between 1 MHZ to 30 MHz can be used. Customers using the 32 kHz oscillator must connect a 10-M resistor in parallel with the 32 kHz crystal. For a complete list of related documentation, click here. Selection Guide Part Number Outputs Input Frequency Range Output Frequency Range Specifics 10 MHz25 MHz (external crystal) 76.923 kHz100 MHz (5 V) Factory programmable CY2291 8 1 MHz30 MHz (reference clock) 76.923 kHz80 MHz (3.3 V) Commercial temperature 10 MHz25 MHz (external crystal) 76.923 kHz90 MHz (5 V) Field programmable CY2291F 8 1 MHz30 MHz (reference clock) 76.923 kHz66.6 MHz (3.3 V) Commercial temperature Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07189 Rev. *K Revised May 31, 2017CY2291 Logic Block Diagram 32XIN 32K OSC. 32XOUT XTALIN OSC. XBUF XTALOUT CPLL /1,2,4 (8 BIT) CPUCLK S0 S1 CLKA S2/SUSPEND UPLL CLKB /1,2,4,8 (10 BIT) CLKC /1,2,3,4,5,6 /8,10,12,13 SPLL CLKD /20,24,26,40 /48,52,96,104 (8 BIT) /2,3,4 CLKF CONFIG EPROM SHUTDOWN/ OE Document Number: 38-07189 Rev. *K Page 2 of 16 MUX