CY29973 3.3V 125-MHz Multi-Output Zero Delay Buffer Features Output Frequency up to 125 MHz Spread Spectrum Compatible 12 Clock Outputs: Frequency Configurable Glitch-free Output Clocks Transitioning 350 ps max. Output to Output Skew 3.3V Power Supply Configurable Output Disable Pin Compatible with MPC973 Two Reference Clock Inputs for Dynamic Toggling Industrial Temperature Range: - 40C to +85C Oscillator or PECL Reference Input 52-Pin TQFP Package 1 Table 1. Frequency Table VC0 SEL FB SEL2 FB SEL1 FB SEL0 F VC0 00 00 8x 00 01 12x 00 10 16x 00 11 20x 01 00 16x 01 01 24x 01 10 32x 01 11 40x 10 00 4x 10 01 6x 10 10 8x 10 11 10x 11 00 8x 11 01 12x 11 10 16x 11 11 20x Note < 480 MHz. 1. x = the reference input frequency, 200 MHz < F VCO Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 38-07291 Rev. *C Revised September 09, 2008 + Feedback SELB1 FB SEL1 SELB0 SYNC SELA1 VSS SELA0 QC0 QA3 VDDC VDDC QC1 QA2 SELC0 VSS SELC1 QA1 QC2 VDDC VDDC QA0 QC3 VSS VSS VCO SEL INV CLK CY29973 Logic Block Diagram PECL CLK PECL CLK VCO SEL PLL EN REF SEL Sync D Q QA0 Frz Phase 0 VCO TCLK0 0 QA1 Detector 1 1 TCLK1 LPF QA2 TCLK SEL QA3 FB IN Sync D Q QB0 Frz QB1 QB2 FB SEL2 QB3 MR /OE Sync D Q QC0 Power-On Frz Reset /4, /6, /8, /12 QC1 /4, /6, /8, /10 Sync 2 SELA(0,1) D Q QC2 /2, /4, /6, /8 Frz QC3 2 SELB(0,1) 0 Sync D Q FB OUT /4, /6, /8, /10 2 /2 1 Frz SELC(0,1) Sync Pulse Sync 2 D Q SYNC FB SEL(0,1) Data Generator Frz SCLK Output Disable 12 Circuitry SDATA INV CLK Pinouts 52 51 50 49 48 47 46 45 44 43 42 41 40 VSS VSS 1 39 MR /OE QB0 2 38 VDDC SCLK 3 37 QB1 SDATA 4 36 FB SEL2 VSS 5 35 PLL EN 6 34 QB2 VDDC REF SEL 7 33 CY29973 QB3 TCLK SEL 8 32 9 31 FB IN TCLK0 TCLK1 10 30 VSS PECL CLK 11 29 FB OUT 12 28 VDDC PECL CLK 13 27 FB SEL0 VDD 14 15 16 17 18 19 20 21 22 23 24 25 26 Document : 38-07291 Rev. *C Page 2 of 9 + Feedback