Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY62157H MoBL 8-Mbit (512K words 16-bit) Static RAM with Error-Correcting Code (ECC) 8-Mbit (512K words 16-bit) Static RAM with Error-Correcting Code (ECC) Data writes are performed by asserting the Write Enable input Features (WE LOW), and providing the data and address on device data (I/O through I/O ) and address (A through A ) pins Ultra-low standby current 0 15 0 18 respectively. The Byte High/Low Enable (BHE, BLE) inputs Typical standby current: 5.5 A control byte writes, and write data on the corresponding I/O lines Maximum standby current: 16 A to the memory location specified. BHE controls I/O through 8 High speed: 45 ns I/O and BLE controls I/O through I/O . 15 0 7 Data reads are performed by asserting the Output Enable (OE) Voltage range: 2.2 V to 3.6 V input and providing the required address on the address lines. Embedded Error-Correcting Code (ECC) for single-bit error Read data is accessible on I/O lines (I/O through I/O ). Byte 0 15 correction accesses can be performed by asserting the required byte enable signal (BHE, BLE) to read either the upper byte or the 1.0 V data retention lower byte of data from the specified address location. Transistor-transistor logic (TTL) compatible inputs and outputs All I/Os (I/O through I/O ) are placed in a high impedance state 0 15 when the device is deselected (CE HIGH / CE LOW for dual Available in Pb-free 48-ball VFBGA and 48-pin TSOP I 1 2 chip enable device), or control signals are de-asserted (OE, BLE, packages BHE). Functional Description These devices also have a unique Byte Power down feature, where, if both the Byte Enables (BHE and BLE) are disabled, the CY62157H is a high-performance CMOS low-power (MoBL) devices seamlessly switch to standby mode irrespective of the SRAM device with Embedded Error-Correcting Code. ECC logic state of the chip enable(s), thereby saving power. can detect and correct single bit error in accessed location. The CY62157H device is available in a Pb-free 48-ball VFBGA This device is offered in dual chip enable option. Dual chip and 48-pin TSOP I packages. The logic block diagram is on enable devices are accessed by asserting both chip enable page 2. inputs CE as LOW and CE as HIGH. 1 2 Product Portfolio Power Dissipation Features and Options Operating I , (mA) CC Standby, I (A) Product Range V Range (V) Speed (ns) SB2 (see the Pin CC f = f max Configurations 1 1 Typ Max Typ Max section) CY62157H30 Dual Chip Industrial 2.2 V3.6 V 45 29 36 5.5 16 Enable Note 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V =3V (for V range of 2.2 V3.6 V), T = 25 C. CC CC A Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-88316 Rev. *E Revised February 8, 2018