Product Information


CY7C09569V-83BBC electronic component of Infineon

SRAM Chip Sync Dual 3.3V 576K-bit 16K x 36 18ns/6ns 172-Pin FBGA

Manufacturer: Infineon
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges

Price (USD)

1: USD 118.4714 ea
Line Total: USD 118.4714

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - Global Stock

Ships to you between Fri. 06 Oct to Thu. 12 Oct

MOQ : 1
Multiples : 1
1 : USD 118.4714
10 : USD 106.6171

Product Category
Memory Size
576 kb it
16 K X 36
Access Time
6 ns
Maximum Clock Frequency
83 MHz
Interface Type
Supply Voltage - Max
3.465 V
Supply Voltage - Min
3.135 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
Package / Case
FBGA - 172
Supply Current - Max
360 mA
Data Rate
Memory Type
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CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3 V, 16K/32K 36 FLEx36 Synchronous Dual-Port Static RAM CY7C09569V CY7C09579V 3.3 V, 16K/32K 36 FLEx36 Synchronous Dual-Port Static RAM 3.3 V, 16K/32K 36 FLEx36 Synchronous Dual-Port Static RAM Features Functional Description True dual-ported memory cells which allow simultaneous The CY7C09569V and CY7C09579V are high-speed 3.3V access of the same memory location synchronous CMOS 16K and 32K 36 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous Two flow-through/pipelined devices access for reads and writes to any location in memory. Registers 16K 36 organization (CY7C09569V) on control, address, and data lines allow for minimal set-up and 32K 36 organization (CY7C09579V) hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid t = 5 ns (pipelined). CD2 0.25-micron CMOS for optimum speed/power Flow-through mode can also be used to bypass the pipelined Three modes output register to eliminate access latency. In flow-through mode data will be available t = 12.5 ns after the address is clocked Flow-through CD1 into the device. Pipelined output or flow-through mode is Pipelined selected via the FT/Pipe pin. Burst Each port contains a burst counter on the input address register. Bus-matching capabilities on right port ( 36 to 18 or 9) The internal write pulse width is independent of the external R/W LOW duration. The internal write pulse is self-timed to allow the Byte-select capabilities on left port shortest possible cycle times. 100 MHz pipelined operation A HIGH on CE for one clock cycle will power down the internal High-speed clock to data access 5/6 ns circuitry to reduce the static power consumption. In the pipelined mode, one cycle is required with CE LOW to reactivate the 3.3 V low operating power outputs. Active = 250 mA (typical) Counter Enable Inputs are provided to stall the operation of the Standby = 10 A (typical) address input and utilize the internal address generated by the Fully synchronous interface for ease of use internal counter for fast interleaved memory applications. A ports burst counter is loaded with the ports Address Strobe Burst counters increment addresses internally (ADS). When the ports Count Enable (CNTEN) is asserted, the Shorten cycle times address counter will increment on each LOW-to-HIGH transition Minimize bus noise of that ports clock signal. This will read/write one word from/into Supported in flow-through and pipelined modes each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop Counter address read back via I/O lines back to the start. Counter Reset (CNTRST) is used to reset the Single chip enable burst counter. Parts are available in 144-pin Thin Quad Plastic Flatpack Automatic power-down (TQFP), 144-pin Pb-free Thin Quad Plastic Flatpack (TQFP) and Commercial and industrial temperature ranges 172-ball Ball Grid Array (BGA) packages. Compact package For a complete list of related documentation, click here. 144-pin TQFP (20 20 1.4 mm) 144-pin Pb-free TQFP (20 20 1.4 mm) 172-ball BGA (15 15 0.51 mm (1.0 mm pitch)) Selection Guide CY7C09569V / CY7C09579V Description Unit -100 -83 f (pipelined) 100 83 MHz MAX2 Maximum access time (clock to data, pipelined) 5 6 ns Typical operating current I 250 240 mA CC Typical standby current for I (both ports TTL level) 30 25 mA SB1 Typical standby current for I (both ports CMOS level) 10 10 A SB3 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-06054 Rev. *L Revised August 1, 2017CY7C09569V CY7C09579V Logic Block Diagram R/W L R/W R OE L Left OE Right R B B Port Port 0 3 Control CE Control R CE L Logic Logic FT/Pipe FT/Pipe R L BE 9 9 I/O I/O 0L 8L 9 9 I/O I/O 9/18/36 9L 17L I/O Bus I/O I/O R Control 9 Match Control 9 I/O I/O 18L 26L 9 9 BM I/O I/O 27L 35L SIZE 1 14/15 14/15 1 A A 0 13/14R A A 0 13/14L Counter/ Counter/ CLK CLK L R Address True Dual-Ported Address ADS ADS L R Register RAM Array Register CNTEN CNTEN L R Decode Decode CNTRST CNTRST L R Note 1. A A for 16K A A for 32K devices. 0 13 0 14 Document Number: 38-06054 Rev. *L Page 2 of 33

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory
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