CY7C1460AV25
CY7C1462AV25
36-Mbit (1 M 36/2 M 18)
Pipelined SRAM with NoBL Architecture
36-Mbit (1 M 36/2 M 18) Pipelined SRAM with NoBL Architecture
Features Functional Description
The CY7C1460AV25/CY7C1462AV25 are 2.5V,
Pin-compatible and functionally equivalent to ZBT
1 M 36/2 M 18 synchronous pipelined burst SRAMs with No
Supports 250-MHz bus operations with zero wait states Bus Latency (NoBL logic, respectively. They are designed
to support unlimited true back-to-back read/write operations with
Available speed grades are 250, 200 and 167 MHz
no wait states. The CY7C1460AV25/CY7C1462AV25 are
Internally self-timed output buffer control to eliminate the need
equipped with the advanced NoBL logic required to enable
to use asynchronous OE
consecutive read/write operations with data being transferred on
every clock cycle. This feature dramatically improves the
Fully registered (inputs and outputs) for pipelined operation
throughput of data in systems that require frequent write/read
Byte Write capability
transitions. The CY7C1460AV25/CY7C1462AV25 are
pin-compatible and functionally equivalent to ZBT devices.
2.5 V core power supply
All synchronous inputs pass through input registers controlled by
2.5 V I/O power supply
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
Fast clock-to-output times
input is qualified by the clock enable (CEN) signal, which when
2.6 ns (for 250-MHz device)
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the byte write selects
Clock enable (CEN) pin to suspend operation
(BW BW for CY7C1460AV25 and BW BW for
a d a b
Synchronous self-timed writes
CY7C1462AV25) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
CY7C1460AV25, CY7C1462AV25 available in
JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and Three synchronous chip enables (CE , CE , CE ) and an
1 2 3
non Pb-free 165-ball FBGA package. asynchronous output enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
IEEE 1149.1 JTAG-Compatible Boundary Scan
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Burst capability linear or interleaved burst order
For a complete list of related documentation, click here.
ZZ sleep mode option and stop clock option
Logic Block Diagram CY7C1460AV25
ADDRESS
A0, A1, A
REGISTER 0 A1 A1'
D1 Q1
A0 BURST A0'
D0 Q0
MODE LOGIC
ADV/LD
CLK C
C
CEN
WRITE ADDRESS WRITE ADDRESS
REGISTER 1 REGISTER 2
O
O
S
U
D U
T
E
T
A
P
N P
U T
U
S T
ADV/LD A
T
WRITE REGISTRY E
R
MEMORY
AND DATA COHERENCY S B
BWa WRITE E DQs
ARRAY
CONTROL LOGIC G U
DRIVERS T
A DQPa
BWb
I F
BWc E DQPb
M S
F
BWd
T E DQPc
P E
E
R R DQPd
S
WE R
S
I
S
E N E
G
INPUT INPUT
E E
REGISTER 1 REGISTER 0
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
ZZ
CONTROL
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-05354 Rev. *L Revised September 11, 2015CY7C1460AV25
CY7C1462AV25
Logic Block Diagram CY7C1462AV25
ADDRESS
A0, A1, A
REGISTER 0
A1 A1'
D1 Q1
A0 BURST A0'
D0 Q0
MODE LOGIC
ADV/LD
CLK C
C
CEN
WRITE ADDRESS WRITE ADDRESS
REGISTER 1 REGISTER 2
O
O
U
U
T
T
P
S D P
U
E U
ADV/LD A
T
N T
T
WRITE REGISTRY S
A
R
MEMORY
E B
AND DATA COHERENCY
DQs
BWa WRITE E
ARRAY U
S
CONTROL LOGIC
G
DRIVERS A F
T DQPa
I
M F
E
BWb
S DQPb
P E E
T
S R
R
E
S
I
R
N
WE
S
G
E E
INPUT INPUT
E E
REGISTER 1 REGISTER 0
OE
READ LOGIC
CE1
CE2
CE3
Sleep
ZZ
Control
Document Number: 38-05354 Rev. *L Page 2 of 31