Product Information

CY7C1461KV33-133AXC

CY7C1461KV33-133AXC electronic component of Infineon

Datasheet
SRAM Sync SRAMs
Manufacturer: Infineon
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

144: USD 49.95 ea
Line Total: USD 7192.8

0 - Global Stock
MOQ: 144  Multiples: 1
Pack Size: 1

 More Buying Options & Price Grid(s)

Availability Price Quantity
0 - WHS 1


Ships to you between Fri. 10 May to Thu. 16 May

MOQ : 144
Multiples : 1
144 : USD 49.95

0 - WHS 2


Ships to you between Thu. 16 May to Mon. 20 May

MOQ : 1
Multiples : 1
1 : USD 67.045
10 : USD 61.0305
25 : USD 60.674
50 : USD 59.3975
100 : USD 55.315
288 : USD 55.2345
576 : USD 54.395

Read More Specifications

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Memory Size
Organization
Access Time
Maximum Clock Frequency
Maximum Operating Temperature
Minimum Operating Temperature
Packaging
Memory Type
Type
Brand
Moisture Sensitive
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Additional Infomation About Product

CY7C1461KV33 CY7C1463KV33 36-Mbit (1M 36/2M 18) Flow-Through SRAM with NoBL Architecture 36-Mbit (1M 36/2M 18) Flow-Through SRAM with NoBL Architecture Features Functional Description No Bus Latency (NoBL) architecture eliminates dead The CY7C1461KV33/CY7C1463KV33 are 3.3V, cycles between write and read cycles 1M36/2M18 Synchronous Flow-Through Burst SRAMs designed specifically to support unlimited true back-to-back read Supports up to 133 MHz bus operations with zero wait states and write operations without the insertion of wait states. The Data is transferred on every clock CY7C1461KV33/CY7C1463KV33 is equipped with the advanced NoBL logic required to enable consecutive read and write Pin compatible and functionally equivalent to ZBT devices operations with data being transferred on every clock cycle. This Internally self timed output buffer control to eliminate the need feature dramatically improves the throughput of data through the to use OE SRAM, especially in systems that require frequent write-read transitions. Registered inputs for flow through operation All synchronous inputs pass through input registers controlled by Byte write capability the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends 3.3 V and 2.5 V I/O power supply operation and extends the previous clock cycle. Maximum Fast clock-to-output times access delay from the clock rise is 6.5 ns (133 MHz device). 6.5 ns (for 133-MHz device) Write operations are controlled by the two or four Byte Write Clock Enable (CEN) pin to enable clock and suspend operation Select (BW ) and a Write Enable (WE) input. All writes are X conducted with on-chip synchronous self timed write circuitry. Synchronous self timed writes Three synchronous Chip Enables (CE , CE , CE ) and an 1 2 3 Asynchronous Output Enable asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, CY7C1461KV33, CY7C1463KV33 available in the output drivers are synchronously tri-stated during the data JEDEC-standard Pb-free 100-pin TQFP packages portion of a write sequence. Three chip enables for simple depth expansion Automatic power down feature available using ZZ mode or CE deselect Burst capability linear or interleaved burst order Low standby power Selection Guide Description 133 MHz Unit Maximum access time 6.5 ns Maximum operating current 18 150 mA 36 170 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-66681 Rev. *G Revised June 7, 2016 CY7C1461KV33 CY7C1463KV33 Logic Block Diagram CY7C1461KV33 ADDRESS A0, A1, A A1 REGISTER A1 D1 Q1 A0 A0 D0 Q0 MODE BURST CE ADV/LD CLK C LOGIC C CEN WRITE ADDRESS REGISTER O U T P D S U A E T T ADV/LD N A S B MEMORY BW A WRITE E WRITE REGISTRY S U ARRAY DQs DRIVERS F BW B AND DATA COHERENCY T DQP A A F E CONTROL LOGIC DQP B BW C M E E DQP C P R R BW D DQP D S S I WE E N G INPUT E REGISTER OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Document Number: 001-66681 Rev. *G Page 2 of 23

HS Compliance

Tariff Desc

8542.32.00 31 No ..Random Access Memory (RAM) including Single Inline Memory Modules (SIMMS), Dual Inline Memory Modules (DIMMS), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SD RAM), Rambus Dynamic Random Access Memory (RD RAM) and other similar memory

Infineon may also be referenced as

CYP
Cypress
Cypress / Spansion
CYPRESS SEMI
Cypress Semicon
Cypress Semiconductor
Cypress Semiconductor Corp
INF
INFINEON
Infineon IR
INFINEON (CYPRESS)
Infineon (IRF)
Infineon / Cypress
Infineon / IR
INFINEON TECH ICs
Infineon Technologies
INFINEON TECHNOLOGIES AG
Infineon Technologies Americas Corp.
Infinite Power Solutions
INTERNATIONAL RECTIF
INTERNATIONAL RECTIFIER
International Rectifier HiRel Products
INTL RECTIFIER
IR
IRH
Ramtron
Ramtron / Cypress Semiconductor
Ramtron International Corp
SP9
SPANSION

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