CY7C1471BV25 72-Mbit (2 M 36) Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M 36/1 M 72) Flow-Through SRAM with NoBL Architecture Features Functional Description No Bus Latency (NoBL) architecture eliminates dead The CY7C1471BV25, is 2.5 V, 2M36 synchronous flow cycles between write and read cycles through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion Supports up to 133 MHz bus operations with zero wait states of wait states. The CY7C1471BV25, is equipped with the advanced No Bus Latency (NoBL) logic required to enable Data transfers on every clock consecutive read or write operations with data transferred on Pin compatible and functionally equivalent to ZBT devices every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that Internally self timed output buffer control to eliminate the need require frequent write-read transitions. to use OE All synchronous inputs pass through input registers controlled by Registered inputs for flow through operation the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends Byte Write capability operation and extends the previous clock cycle. Maximum 2.5-V I/O supply (V ) DDQ access delay from the clock rise is 6.5 ns (133-MHz device). Fast clock-to-output times Write operations are controlled by two or four Byte Write Select (BW ) and a Write Enable (WE) input. All writes are conducted 6.5 ns (for 133-MHz device) X with on-chip synchronous self timed write circuitry. Clock Enable (CEN) pin to enable clock and suspend operation Three synchronous Chip Enables (CE , CE , CE ) and an 1 2 3 Synchronous self timed writes asynchronous Output Enable (OE) provide easy bank selection and output tristate control. To avoid bus contention, the output Asynchronous Output Enable (OE) drivers are synchronously tristated during the data portion of a write sequence. CY7C1471BV25 available in JEDEC-standard Pb-free 100-pin TQFP package. For a complete list of related documentation, click here. Three Chip Enables (CE , CE , CE ) for simple depth 1 2 3 expansion. Automatic power down feature available using ZZ mode or CE deselect. Burst Capability linear or interleaved burst order Low standby power Selection Guide Description 133 MHz Unit Maximum Access Time 6.5 ns Maximum Operating Current 305 mA Maximum CMOS Standby Current 120 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-15013 Rev. *N Revised May 11, 2016CY7C1471BV25 Logic Block Diagram CY7C1471BV25 ADDRESS A0, A1, A A1 REGISTER A1 D1 Q1 A0 A0 D0 Q0 MODE BURST CE ADV/LD CLK C LOGIC C CEN WRITE ADDRESS REGISTER O U T P D S A U E T T N ADV/LD A S B MEMORY BW A WRITE E U WRITE REGISTRY S ARRAY DQs DRIVERS F BW B AND DATA COHERENCY T DQP A A F E CONTROL LOGIC DQP B BW C M E E DQP C P R R BW D DQP D S I S WE E N G INPUT E REGISTER OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Document Number: 001-15013 Rev. *N Page 2 of 22