CY7C2663KV18/CY7C2665KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 144-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports With Read Cycle Latency of 2.5 cycles: Supports concurrent transactions CY7C2663KV18: 8M 18 550-MHz clock for high bandwidth CY7C2665KV18: 4M 36 Four-word burst for reducing address bus frequency Functional Description Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz The CY7C2663KV18, and CY7C2665KV18 are 1.8V Available in 2.5-clock cycle latency synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture Two input clocks (K and K) for precise DDR timing consists of two separate ports: the read port and the write port to Static random access memory (SRAM) uses rising edges access the memory array. The read port has dedicated data only outputs to support read operations and the write port has Echo clocks (CQ and CQ) simplify data capture in high-speed dedicated data inputs to support write operations. QDR II+ systems architecture has separate data inputs and data outputs to completely eliminate the need to turnaround the data bus that Data valid pin (QVLD) to indicate valid data on the output exists with common I/O devices. Each port is accessed through On-die termination (ODT) feature a common address bus. Addresses for read and write addresses Supported for D , BWS , and K/K inputs are latched on alternate rising edges of the input (K) clock. x:0 x:0 Accesses to the QDR II+ read and write ports are completely Single multiplexed address input bus latches address inputs independent of one another. To maximize data throughput, both for read and write ports read and write ports are equipped with DDR interfaces. Each address location is associated with four 18-bit words Separate port selects for depth expansion (CY7C2663KV18), or 36-bit words (CY7C2665KV18) that burst Synchronous internally self-timed writes sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input Quad data rate (QDR ) II+ operates with 2.5-cycle read latency clocks (K and K), memory bandwidth is maximized while when DOFF is asserted high simplifying system design by eliminating bus turn arounds. Operates similar to QDR I device with 1 cycle read latency when These devices have an ODT feature supported for D , DOFF is asserted low x:0 BWS , and K/K inputs, which helps eliminate external x:0 Available in 18, and 36 configurations termination resistors, reduce cost, reduce board area, and Full data coherency, providing most current data simplify board routing. 1 Core V = 1.8 V 0.1 V I/O V = 1.4 V to V Depth expansion is accomplished with port selects, which DD DDQ DD enables each port to operate independently. Supports both 1.5 V and 1.8 V I/O supply All synchronous inputs pass through input registers controlled by High-speed transceiver logic (HSTL) inputs and variable drive the K or K input clocks. All data outputs pass through output HSTL output buffers registers controlled by the K or K input clocks. Writes are Available in 165-ball fine-pitch ball grid array (FBGA) package conducted with on-chip synchronous self-timed write circuitry. (15 17 1.4 mm) For a complete list of related documentation, click here. Offered in both Pb-free and non Pb-free packages JTAG 1149.1 compatible test access port Phase locked loop (PLL) for accurate data placement Selection Guide Description 550 MHz 450 MHz Unit Maximum operating frequency 550 450 MHz Maximum operating current 18 1090 940 mA 36 1520 1290 Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V = 1.4 V to V . DDQ DD Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-44141 Rev. *Q Revised November 24, 20172M 18 Array 1M 36 Array 2M 18 Array 1M 36 Array 2M 18 Array 1M 36 Array 2M 18 Array 1M 36 Array CY7C2663KV18/CY7C2665KV18 Logic Block Diagram CY7C2663KV18 18 D 17:0 Write Write Write Write 21 Address A Reg Reg Reg Reg (20:0) Register 21 Address A (20:0) Register K RPS Control CLK K Logic Gen. DOFF Read Data Reg. CQ 72 V 36 REF 18 CQ Reg. Reg. Control WPS 18 Logic 18 18 36 BWS Q Reg. 1:0 17:0 18 QVLD Logic Block Diagram CY7C2665KV18 36 D 35:0 Write Write Write Write 20 Address A Reg Reg Reg Reg (19:0) Register 20 Address A (19:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 144 V 72 REF CQ 36 Reg. Reg. Control WPS 36 Logic 36 72 36 BWS Q Reg. 3:0 35:0 36 QVLD Document Number: 001-44141 Rev. *Q Page 2 of 31 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode