CY7C4121KV13/CY7C4141KV13 144-Mbit QDR-IV HP SRAM 144-Mbit QDR-IV HP SRAM Features Configurations 144-Mbit density (8M 18, 4M 36) CY7C4121KV13 8M 18 1 CY7C4141KV13 4M 36 Total Random Transaction Rate of 1334 MT/s Maximum operating frequency of 667 MHz Functional Description Read latency of 5.0 clock cycles and write latency of 3.0 clock The QDR-IV HP (High-Performance) SRAM is a cycles high-performance memory device that has been optimized to maximize the number of random transactions per second by the Two-word burst on all accesses use of two independent bidirectional data ports. Dual independent bidirectional data ports These ports are equipped with DDR interfaces and designated Double data rate (DDR) data ports as port A and port B respectively. Accesses to these two data Supports concurrent read/write transactions on both ports ports are concurrent and completely independent of each other. Access to each port is through a common address bus running Single address port used to control both data ports at DDR. The control signals are running at SDR and determine DDR address signaling if a read or write should be performed. Single data rate (SDR) control signaling There are three types of differential clocks: High-speed transceiver logic (HSTL) and stub series (CK, CK ) for address and command clocking terminated logic (SSTL) compatible signaling (JESD8-16A compliant) (DKA, DKA , DKB, DKB ) for data input clocking I/O V = 1.2 V 50 mV or 1.25 V 50 mV DDQ (QKA, QKA , QKB, QKB ) for data output clocking Pseudo open drain (POD) signaling (JESD8-24 compliant) Addresses for port A are latched on the rising edge of the input I/O V = 1.1 V 50 mV or 1.2 V 50 mV DDQ clock (CK), and addresses for port B are latched on the falling edge of the input clock (CK). Core voltage V = 1.3 V 40 mV The QDR-IV HP SRAM device is offered in a two-word burst DD option and is available in 18 and 36 bus width configurations. On-die termination (ODT) For a 18 bus width configuration, there are 22 address bits, and Programmable for clock, address/command, and data inputs for a 36 bus width configuration, there are 21 address bits Internal self-calibration of output impedance through ZQ pin respectively. Bus inversion to reduce switching noise and power An on-chip ECC circuitry detects and corrects all single-bit memory errors, including those induced by soft-error events, Programmable on/off for address and data such as cosmic rays and alpha particles. The resulting SER of Address bus parity error protection these devices is expected to be less than 0.01 FITs/Mb, a four-order-of-magnitude improvement over previous generation Training sequence for per-bit deskew SRAMs. On-chip error correction code (ECC) to reduce soft error rate For a complete list of related resources, click here. (SER) JTAG 1149.1 test access port (JESD8-26 compliant) 1.3-V LVCMOS signaling Available in 361-ball FCBGA Pb-free package (21 21 mm) Selection Guide QDR-IV QDR-IV QDR-IV Description Unit 1334 (MT/s) 1266 (MT/s) 1200 (MT/s) Maximum operating frequency 667 633 600 MHz Maximum operating current 18 2500 2400 2300 mA 36 3200 2950 2700 Note 1. Random Transaction Rate (RTR) is defined as the number of fully random memory accesses (reads or writes) that can be performed on the memory. RTR is measured in million transactions per second. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-79343 Rev. *Q Revised August 4, 2017 CY7C4121KV13/CY7C4141KV13 Logic Block Diagram CY7C4121KV13 Document Number: 001-79343 Rev. *Q Page 2 of 45