Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C924ADX 200 MBaud HOTLink Transceiver 200 MBaud HOTLink Transceiver sponding CY7C924ADX parts. As a second generation HOTLink Features device, the CY7C924ADX provides enhanced levels of Second generation HOTLink technology technology, functionality, and integration over the field proven CY7B923/933 HOTLink. Fibre channel and ESCON compliant 8B/10B The transmit section of the CY7C924ADX HOTLink can be encoder/decoder configured to accept either 8 or 10 bit data characters on each 10 or 12-bit preencoded data path (raw mode) clock cycle, and stores the parallel data in an internal Transmit FIFO. Data is read from the Transmit FIFO and is encoded using 8 or 10-bit encoded data transport (using 8B/10B coding) an embedded 8B/10B encoder to improve its serial transmission Synchronous or asynchronous TTL parallel interface characteristics. These encoded characters are then serialized and output from two Positive ECL (PECL) compatible differential UTOPIA compatible host bus interface transmission line drivers at a bit rate of 10 or 12 times the character rate. Embedded/bypassable 256-character synchronous FIFOs The receive section of the CY7C924ADX HOTLink accepts a Integrated support for daisy-chain and ring topologies serial bit stream from one of two PECL compatible differential Domain or individual destination device addressing line receivers and, using a completely integrated PLL Clock Synchronizer, recovers the timing information necessary for data 50 to 200 MBaud serial signaling rate reconstruction. The recovered bit stream is deserialized and framed into characters, 8B/10B decoded, and checked for trans- Internal PLLs with no external PLL components mission errors. Recovered decoded characters are recon- Dual differential PECL compatible serial inputs structed into either 8 or 10 bit data characters, written to an internal Receive FIFO, and presented to the destination host Dual differential PECL compatible serial outputs system. Compatible with fiber optic modules and copper cables Systems that present externally encoded or scrambled data at the parallel interface may bypass the integrated 8B/10B Built-in self-test (BIST) for link testing encoder/decoder. The embedded FIFOs may also be bypassed Link quality indicator to create a reference locked serial transmission link. For those systems requiring even greater FIFO storage capability, external Single +5.0 V 10% supply FIFOs may directly couple to the CY7C924ADX device through 100-pin TQFP the parallel interface without additional glue-logic. You can configure the TTL parallel I/O interface as either a FIFO 0.35 CMOS technology (configurable for UTOPIA emulation or for depth expansion Pb-free package available through external FIFOs) or as a pipeline register extender. The FIFO configurations are optimized for transport of Functional Description time-independent (asynchronous) 8 or 10 bit character oriented The 200 MBaud CY7C924ADX HOTLink Transceiver is a data across a link. A Built-In Self-Test (BIST) pattern generator point-to-point communications building block allowing the and checker permits at-speed testing of the high speed serial transfer of data over high speed serial links (optical fiber, data paths in both the transmit and receive sections, and across balanced, and unbalanced copper transmission lines) at speeds the interconnecting links. HOTLink devices are ideal for a variety ranging between 50 and 200 MBaud. The transmit section of applications where parallel interfaces can be replaced with accepts parallel data of selectable width and converts it to serial high speed, point-to-point serial links. Some applications include data, while the receiver section accepts serial data and converts interconnecting workstations, backplanes, servers, mass it to parallel data of selectable width. Figure 1 illustrates typical storage, and video transmission equipment. connections between two independent host systems and corre- Figure 1. HOTLink System Connections Transmit Data Data Receive Serial Link Control Control CY7C924ADX CY7C924ADX Status Status Serial Link Data Receive Transmit Data Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-02008 Rev. *J Revised July 18, 2019 System Host FIFO FIFO Transmit Receive Encoder Decoder 8B/10B 8B/10B Framer Serializer Deserializer Deserializer Serializer Framer 8B/10B 8B/10B Decoder Encoder Receive Transmit FIFO FIFO System Host