Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comPSoC 4: PSoC 4000S Datasheet Programmable System-on-Chip (PSoC) General Description PSoC 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm Cortex-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4000S product family is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4000S products are upward compatible with members of the PSoC 4 platform for new applications and design needs. Timing and Pulse-Width Modulation Features Five 16-bit timer/counter/pulse-width modulator (TCPWM) 32-bit MCU Subsystem blocks 48-MHz Arm Cortex-M0+ CPU with single-cycle multiply Center-aligned, Edge, and Pseudo-random modes Up to 32 KB of flash with Read Accelerator Comparator-based triggering of Kill signals for motor drive and Up to 4 KB of SRAM other high-reliability digital logic applications Programmable Analog Up to 36 Programmable GPIO Pins Single-slope 10-bit ADC function provided by Capacitance sensing block 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, 32-pin TQFP, and 25-ball WLCSP packages Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin Any GPIO pin can be CapSense, analog, or digital Two low-power comparators that operate in Deep Sleep Drive modes, strengths, and slew rates are programmable low-power mode Clock Sources Programmable Digital 32-kHz Watch Crystal Oscillator (WCO) Programmable logic blocks allowing Boolean operations to be performed on port inputs and outputs 2% Internal Main Oscillator (IMO) 32-kHz Internal Low-power Oscillator (ILO) Low-Power 1.71-V to 5.5-V Operation Deep Sleep mode with operational analog and 2.5 A digital ModusToolbox Software system current Comprehensive collection of multi-platform tools and software libraries Capacitive Sensing Includes board support packages (BSPs), peripheral driver Cypress CapSense Sigma-Delta (CSD) provides best-in-class library (PDL), and middleware such as CapSense signal-to-noise ratio (SNR) (>5:1) and water tolerance Cypress-supplied software component makes capacitive PSoC Creator Design Environment sensing design easy Integrated development environment (IDE) provides schematic Automatic hardware tuning (SmartSense) design entry and build, with analog and digital automatic routing Application programming interface (API) Components for all LCD Drive Capability fixed-function and programmable peripherals LCD segment drive capability on GPIOs Industry-Standard Tool Compatibility Serial Communication After schematic entry, development can be done with Two independent run-time reconfigurable Serial Arm-based industry-standard development tools 2 Communication Blocks (SCBs) with re-configurable I C, SPI, or UART functionality Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00123 Rev. *N Revised December 23, 2020