Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY9B520M Series 32-bit Arm Cortex -M3 FM3 Microcontroller The CY9B520M Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the Arm Cortex -M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions 2 such as various timers, ADCs, DACs and Communication Interfaces (USB, CAN, UART, CSIO, I C, LIN). The products which are described in this data sheet are placed into TYPE9 product categories in FM3 Family Peripheral Manual. Features USB device 32-bit Arm Cortex -M3 Core USB2.0 Full-Speed supported Processor version: r2p1 Max 6 EndPoint supported Up to 72 MHz Frequency Operation EndPoint 0 is control transfer Integrated Nested Vectored Interrupt Controller (NVIC): 1 EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or NMI (non-maskable interrupt) and 48 peripheral interrupts Isochronous-transfer and 16 priority levels EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer 24-bit System timer (Sys Tick): System timer for OS task EndPoint 1 to 5 are comprised of Double Buffers. management The size of each endpoint is according to the follows. Endpoint 0, 2 to 5: 64 bytes On-chip Memories Endpoint 1: 256 bytes Flash memory USB host Dual operation Flash memory USB2.0 Full/Low-speed supported Dual Operation Flash memory has the upper bank and the lower bank. Bulk-transfer, interrupt-transfer and Isochronous-transfer So, this series could implement erase, write and read support operations for each bank simultaneously. Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank USB Device connected/dis-connected automatic detection + 16 Kbytes lower bank) Automatic processing of the IN/OUT token handshake Work area: 32 Kbytes (lower bank) packet Read cycle: 0 wait-cycle Max 256-byte packet-length supported Security function for code protection Wake-up function supported SRAM This Series on-chip SRAM is composed of two independent CAN Interface SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus Compatible with CAN Specification 2.0A/B and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. Maximum transfer rate: 1 Mbps SRAM0: Up to 16 Kbytes Built-in 32 message buffer SRAM1: Up to 16 Kbytes Multi-function Serial Interface (Max eight channels) USB Interface 4 channels with 16 steps9-bit FIFO (ch.0/1/3/4), 4 channels The USB interface is composed of Device and Host. without FIFO (ch.2/5/6/7) PLL for USB is built-in, USB clock can be generated by Operation mode is selectable from the followings for each multiplication of Main clock. channel. UART CSIO LIN 2 I C Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-05649 Rev. *F Revised June 18, 2020