IR2118SPBF Infineon

Data Sheet No. PD60146 Rev O IR2117(S)/IR2118(S) & (PbF) SINGLE CHANNEL DRIVER Features Product Summary Floating channel designed for bootstrap operation V 600V max. Fully operational to +600V OFFSET Tolerant to negative transient voltage dV/dt immune I +/- 200 mA / 420 mA O Gate drive supply range from 10 to 20V Undervoltage lockout V 10 - 20V OUT CMOS Schmitt-triggered inputs with pull-down Output in phase with input (IR2117) or out of t (typ.) 125 & 105 ns on/off phase with input (IR2118) Also available LEAD-FREE Packages Description The IR2117/IR2118(S) is a high voltage, high speed power MOSFET and IGBT driver. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS outputs. The output driver fea- tures a high pulse current buffer stage designed for minimum cross-conduction. The floating channel can 8-Lead PDIP 8-Lead SOIC be used to drive an N-channel power MOSFET or IGBT IR2117/IR2118 IR2117S/IR2118S in the high or low side configuration which operates up to 600 volts. Typical Connection IR2117 IR2118 (Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1IR2117(S)/IR2118(S) & (PbF) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figures 5 through 8. Symbol Definition Min. Max. Units V High side floating supply voltage -0.3 625 B V High side floating supply offset voltage V - 25 V + 0.3 S B B V High side floating output voltage V - 0.3 V + 0.3 V HO S B V Logic supply voltage -0.3 25 CC V Logic input voltage -0.3 V + 0.3 IN CC dV /dt Allowable offset supply voltage transient (figure 2) 50 V/ns s P Package power dissipation T +25C (8 lead PDIP) 1.0 D A W (8 lead SOIC) 0.625 Rth Thermal resistance, junction to ambient (8 lead PDIP) 125 JA C/W (8 lead SOIC) 200 T Junction temperature 150 J T Storage temperature -55 150 C S T Lead temperature (soldering, 10 seconds) 300 L Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The V offset rating is tested with all supplies biased at 15V differential. S Symbol Definition Min. Max. Units V High side floating supply absolute voltage V + 10 V + 20 B S S V High side floating supply offset voltage Note 1 600 S V High side floating output voltage V V HO S B V V Logic supply voltage 10 20 CC V Logic input voltage 0 V IN CC T Ambient temperature -40 125 C A Note 1: Logic operational for V of -5 to +600V. Logic state held for V of -5V to -V . (Please refer to the Design Tip S S BS DT97-3 for more details). 2 www.irf.com