IR2301SPBF Infineon

Data Sheet No. PD60201 Rev.D IR2301(S) & (PbF) HIGH AND LOW SIDE DRIVER Features Packages Floating channel designed for bootstrap operation Fully operational to +600V Tolerant to negative transient voltage dV/dt immune 8 Lead PDIP Gate drive supply range from 5 to 20V IR2301 Undervoltage lockout for both channels 3.3V, 5V and 15V input logic compatible Matched propagation delay for both channels Logic and power ground +/- 5V offset. Lower di/dt gate driver for better noise immunity 8 Lead SOIC Outputs in phase with inputs IR2301S Also available LEAD-FREE (PbF) Description 2106/2301//2108//2109/2302/2304 Feature Comparison The IR2301(S) are high voltage, high speed power MOSFET and IGBT drivers with indepen- dent high and low side referenced output channels. Proprietary HVIC and latch immune %& %* & %& 4 CMOS technologies enable ruggedized mono- %& 7 94 lithic construction. The logic input is compatible : %& 74 <94=9 with standard CMOS or LSTTL output, down to %& > %* % 94 : 3.3V logic. The output drivers feature a high %& >4 <94=9 pulse current buffer stage designed for minimum %* 4 : & driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts. Typical Connection (Refer to Lead Assignments for correct pin con- figuration). This/ These diagram(s) show electrical connections only. Please re- fer to our Appli- cation Notes and DesignTips for proper circuit board layout. IR2301 www.irf.com 1( IR2301 S) & (PbF) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V High side floating absolute voltage -0.3 625 B V High side floating supply offset voltage V - 25 V + 0.3 S B B V High side floating output voltage V - 0.3 V + 0.3 HO S B V Low side and logic fixed supply voltage -0.3 25 V CC V Low side output voltage -0.3 V + 0.3 LO CC V Logic input voltage COM - 0.3 V + 0.3 IN CC dV /dt Allowable offset supply voltage transient 50 V/ns S P Package power dissipation T +25C (8 lead PDIP) 1.0 D A W (8 lead SOIC) 0.625 Rth Thermal resistance, junction to ambient (8 lead PDIP) 125 JA C/W (8 lead SOIC) 200 T Junction temperature 150 J C T Storage temperature -50 150 S T Lead temperature (soldering, 10 seconds) 300 L Recommended Operating Conditions The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The V offset rating is tested with all supplies biased at 15V differential. S Symbol Definition Min. Max. Units VB High side floating supply absolute voltage V + 5 V + 20 S S V High side floating supply offset voltage Note 1 600 S V High side floating output voltage V V HO S B V V Low side and logic fixed supply voltage 5 20 CC V Low side output voltage 0 V LO CC V Logic input voltage COM V IN CC T Ambient temperature -40 150 C A Note 1: Logic operational for V of -5 to +600V. Logic state held for V of -5V to -V . (Please refer to the Design Tip S S BS DT97-3 for more details). 2 www.irf.com