IRS21814SPBF Infineon

Data Sheet No. PD60262 IRS2181/IRS21814(S)PbF HIGH AND LOW SIDE DRIVER Features Packages Floating channel designed for bootstrap operation Fully operational to +600 V 14-Lead PDIP 8-Lead PDIP IRS21814 Tolerant to negative transient voltage, dV/dt IRS2181 immune Gate drive supply range from 10 V to 20 V Undervoltage lockout for both channels 3.3 V and 5 V input logic compatible 8-Lead SOIC Matched propagation delay for both channels IRS2181S Logic and power ground +/- 5 V offset Lower di/dt gate driver for better noise immunity Output source/sink current capability 1.4 A/1.8 A 14-Lead SOIC RoHS compliant IRS21814S Description Feature Comparison Cross- The IRS2181/IRS21814 are high Input conduction Deadtime t /t on off Part Ground Pins voltage, high speed power MOSFET logic prevention (ns) (ns) logic and IGBT drivers with independent 2181 COM HIN/LIN no none 180/220 high-side and low-side referenced 21814 VSS/COM output channels. Proprietary HVIC 2183 Internal 400 COM HIN/LIN yes 180/220 21834 Program 400-5000 VSS/COM and latch immune CMOS technolo- 2184 Internal 400 COM IN/SD yes 680/270 gies enable ruggedized monolithic 21844 Program 400-5000 VSS/COM construction. The logic input is com- patible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to 600 V. Typical Connection up to 600 V V CC V V CC B HIN HIN HO TO LIN LIN V S LOAD COM LO up to 600 V IRS2181 IRS21814 HO V V V CC B CC HIN HIN V S TO LOAD LIN LIN (Refer to Lead Assignments for correct pin configuration). These diagrams show V COM V SS SS electrical connections only. Please refer to LO our Application Notes and DesignTips for proper circuit board layout. 1 www.irf.comIRS2181/IRS21814(S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V High-side floating absolute voltage -0.3 620 (Note 1) B V High-side floating supply offset voltage V - 20 V + 0.3 S B B V High-side floating output voltage V - 0.3 V + 0.3 HO S B V Low-side and logic fixed supply voltage -0.3 20 (Note 1) CC V V Low-side output voltage -0.3 V + 0.3 LO CC V Logic input voltage (HIN & LIN) V - 0.3 V + 0.3 IN SS CC V Logic ground (IRS21814 only) V - 20 V + 0.3 SS CC CC dV /dt Allowable offset supply voltage transient 50 V/ns S (8-lead PDIP) 1.0 (8-lead SOIC) 0.625 P Package power dissipation T +25 C D A W (14-lead PDIP) 1.6 (14-lead SOIC) 1.0 (8-lead PDIP) 125 (8-lead SOIC) 200 C/W Rth Thermal resistance, junction to ambient JA (14-lead PDIP) 75 (14-lead SOIC) 120 T Junction temperature 150 J T Storage temperature -50 150 S C T Lead temperature (soldering, 10 seconds) 300 L Note 1: All supplies are fully tested at 25 V and an internal 20 V clamp exists for each supply. Recommended Operating Conditions The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. The V and V offset rating are tested with all supplies biased at a 15 V differential. S SS Symbol Definition Min. Max. Units VB High-side floating supply absolute voltage V + 10 V + 20 S S V High-side floating supply offset voltage Note 2 600 S V High-side floating output voltage V V HO S B V Low-side and logic fixed supply voltage 10 20 CC V V Low-side output voltage 0 V LO CC V Logic input voltage (HIN & LIN) V V IN SS CC V Logic ground (IRS21814 only) -5 5 SS T Ambient temperature -40 125 C A Note 2: Logic operational for V of -5 V to +600 V. Logic state held for V of -5 V to -V . (Please refer to the Design Tip S S BS DT97-3 for more details). www.irf.com 2