The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix MB. However, Cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix CY. How to Check the Ordering Part Number 1. Go to www.cypress.com/pcn. 2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world s most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrupt markets by creating new product categories in record time. To learn more, go to www.cypress.com. MB9A340NB Series 32-bit ARM Cortex -M3 FM3 Microcontroller The MB9A340NB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the ARM Cortex -M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions 2 such as various timers, ADCs, and Communication Interfaces (USB, UART, CSIO, I C). The products which are described in this data sheet are placed into TYPE6 product categories in FM3 Family Peripheral Manual. Features 32-bit ARM Cortex -M3 Core External Bus Interface* Processor version: r2p1 Supports SRAM, NOR Flash memory device Up to 40 MHz Frequency Operation Up to 8 chip selects Integrated Nested Vectored Interrupt Controller (NVIC): 1 8-/16-bit Data width NMI (non-maskable interrupt) and 48 peripheral interrupts Up to 25-bit Address bit and 16 priority levels Maximum area size: Up to 256 Mbytes 24-bit System timer (Sys Tick): System timer for OS task management Supports Address/Data multiplex Supports external RDY function On-chip Memories *: MB9AF341LB, F342LB and F344LB do not support Flash memory External Bus Interface. Dual operation Flash memory USB Interface Dual Operation Flash memory has the upper bank and the The USB interface is composed of Device and Host. lower bank. PLL for USB is built-in, USB clock can be generated by So, this series could implement erase, write and read multiplication of Main clock. operations for each bank simultaneously. USB device Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank) USB2.0 Full-Speed supported Work area: 32 Kbytes (lower bank) Max 6 EndPoint supported Read cycle: 0 wait-cycle EndPoint 0 is control transfer EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or Security function for code protection Isochronous-transfer EndPoint 3 to 5 can select Bulk-transfer or SRAM Interrupt-transfer This Series on-chip SRAM is composed of two independent EndPoint 1 to 5 is comprised of Double Buffers. SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus The size of each endpoint is according to the follows. and D-code bus of Cortex-M3 core. SRAM1 is connected to - Endpoint 0, 2 to 5: 64 bytes System bus. - Endpoint 1: 256 bytes SRAM0: Up to 16 Kbytes USB host SRAM1: Up to 16 Kbytes USB2.0 Full/Low-speed supported Bulk-transfer, interrupt-transfer and Isochronous-transfer support Automatic detection of connected/disconnected USB Device Automatic processing of the IN/OUT token handshake packet Max 256-byte packet-length supported Wake-up function supported Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-05635 Rev.*B Revised July 26, 2017